VLDB 2026 Research / reviewers in the wild / expert
Kotaro Matsuoka
dblp:276/6652
· DBLP profile ↗
6ranked-venue papers
2as first author
6since 2021 · last 2026
0000-0002-6642-1276ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 3 · 3 since 2021Systems, architecture and hardware · 2 · 1 first-author · 2 since 2021Security and privacy · 1 · 1 first-author · 1 since 2021Theory of computation · 1 · 1 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | ArithHomFA: A toolkit for oblivious online STL monitoringabstractIn runtime verification, monitored data often contains sensitive information, and it is critical for a remote monitor to maintain the confidentiality of the monitored data. ArithHomFA is a prototype toolkit for oblivious online monitoring of discrete-time signal temporal logic (STL) . Based on fully homomorphic encryption (FHE) , ArithHomFA enables users to 1) encrypt a sequence of vectors representing a discrete signal, 2) construct a sequence of ciphertexts representing whether the encrypted signal satisfies the given requirement without decryption, and 3) decrypt the resulting ciphertexts. We illustrate the practicality of ArithHomFA through an example of monitoring vehicle behavior. Masaki Waga, Kotaro Matsuoka, Takashi Suwa |
Sci. Comput. Program. | 2 |
| 2024 | HOGE: Homomorphic Gate on An FPGAabstractThis paper proposes HOGE, a new accelerator architecture on FPGA, for the Fully Homomorphic Encryption over the Torus (TFHE). TFHE is one of the FHE schemes that allows arbitrary logical circuits to be evaluated over encrypted ciphertexts. To the best of the our knowledge, HOGE is the first hardware architecture that achieves the evaluation of a complete homomorphic gate with bootstrapping in one commercial hardware device and the proven capability for working with the host machine to evaluate homomorphic logic circuits. HOGE is equipped with the carefully designed resource-efficient four-step radix-32 NTT/INTT architectures that achieve higher parallelism, resulting in an overall lower latency. HOGE is implemented on the Xilinx Alveo U280 platform and demonstrated that the actual performance can be 5 – 6 × faster than the-state-of-the-art CPU implementation of TFHE, carrying out a homomorphic gate within about 1.6ms. Kotaro Matsuoka, Song Bian 0001, Takashi Sato 0001 |
ASPDAC | 1 |
| 2024 | Logic Locking over TFHE for Securing User Data and AlgorithmsabstractThis paper proposes the application of logic locking over TFHE to protect both user data and algorithms, such as input user data and models in machine learning inference applications. With the proposed secure computation protocol algorithm evaluation can be performed distributively on honest-but-curious user computers while keeping the algorithm secure. To achieve this, we combine conventional logic locking for untrusted foundries with TFHE to enable secure computation. By encrypting the logic locking key using TFHE, the key is secured with the degree of TFHE. We implemented the proposed secure protocols for combinational logic neural networks and decision trees using LUT-based obfuscation. Regarding the security analysis, we subjected them to the SAT attack and evaluated their resistance based on the execution time. We successfully configured the proposed secure protocol to be resistant to the SAT attack in all machine learning benchmarks. Also, the experimental result shows that the proposed secure computation involved almost no TFHE runtime overhead in a test case with thousands of gates. Kohei Suemitsu, Kotaro Matsuoka, Takashi Sato 0001, Masanori Hashimoto |
ASPDAC | 2 |
| 2024 | Oblivious Monitoring for Discrete-Time STL via Fully Homomorphic Encryption
Masaki Waga, Kotaro Matsuoka, Takashi Suwa, Naoki Matsumoto, Ryotaro Banno, Song Bian 0001, Kohei Suenaga |
RV | 2 |
| 2022 | Oblivious Online Monitoring for Safety LTL Specification via Fully Homomorphic EncryptionabstractAbstract In many Internet of Things (IoT) applications, data sensed by an IoT device are continuously sent to the server and monitored against a specification. Since the data often contain sensitive information, and the monitored specification is usually proprietary, both must be kept private from the other end. We propose a protocol to conduct oblivious online monitoring—online monitoring conducted without revealing the private information of each party to the other—against a safety LTL specification. In our protocol, we first convert a safety LTL formula into a DFA and conduct online monitoring with the DFA. Based on fully homomorphic encryption (FHE), we propose two online algorithms (Reverse and Block) to run a DFA obliviously. We prove the correctness and security of our entire protocol. We also show the scalability of our algorithms theoretically and empirically. Our case study shows that our algorithms are fast enough to monitor blood glucose levels online, demonstrating our protocol’s practical relevance. Ryotaro Banno, Kotaro Matsuoka, Naoki Matsumoto, Song Bian 0001, Masaki Waga, Kohei Suenaga |
CAV (1) | 2 |
| 2021 | Virtual Secure Platform: A Five-Stage Pipeline Processor over TFHE
Kotaro Matsuoka, Ryotaro Banno, Naoki Matsumoto, Takashi Sato 0001, Song Bian 0001 |
USENIX Security Symposium | 1 |