Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Venkat Sri Sai Ram

dblp:279/3850 · DBLP profile ↗
← Back
1ranked-venue papers
1as first author
1since 2021 · last 2021
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 70% Processor architecture and microarchitecture · 23% Performance modeling and evaluation · 7%

Topics — the 3 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems › memory management › virtual memory
address translation
0.512021
Trident: Harnessing Architectural Resources for All Page Sizes in x86 Processors · MICRO 2021
Memory systems › memory management › virtual memory
huge pages
0.512021
Trident: Harnessing Architectural Resources for All Page Sizes in x86 Processors · MICRO 2021
Memory systems › memory management
virtual memory
0.512021
Trident: Harnessing Architectural Resources for All Page Sizes in x86 Processors · MICRO 2021

Methods — techniques the papers use, named apart from their topics

page size management · 0.5
YearPublicationVenuePosition
2021 Trident: Harnessing Architectural Resources for All Page Sizes in x86 Processors
abstract
Intel and AMD processors have long supported more than one large page sizes – 1GB and 2MB, to reduce address translation overheads for applications with large memory footprints. However, previous works on large pages have primarily focused on 2MB pages, partly due to a lack of evidence on the usefulness of 1GB pages to real-world applications. Consequently, micro-architectural resources devoted to 1GB pages have gone underutilized for a decade.
Venkat Sri Sai Ram, Ashish Panwar, Arkaprava Basu
MICRO1