This paper presents a novel 8-to-12 b, 1-to-20 MSPS Reconfigurable SAR ADC for low power multi-standard systems to avoid multi-ADCs’ integration in SoC designs thus reducing power and area. To enhance power efficiency across varying conversion rates and resolutions, proposed ADC integrates a custom-designed source-degeneration dynamic comparator along with a reconfigurable asynchronous mechanism. Furthermore, to broaden its applicability, the ADC utilizes an optimized window-switching (OWS) scheme to mitigate dynamic and static performance degradation stemming from capacitor array nonlinearity without the need for additional calibration algorithms. The prototype is designed in 40nm CMOS process with 1.2 V supply and occupied an active area of 0.0445mm2. Post-simulation results show that ADC’s 8b 1MSPS mode achieves SNDR of 48.86 dB, SFDR of 64.49 dB and FoMWof 154.5 fJ/conv-step. And 10b 5MSPS achieves SNDR of 60.89 dB, SFDR of 74.23 dB and FoMWof 45.8 fJ/conv-step. 12b 20MSPS achieves SNDR of 70.33 dB, SFDR of 83.59 dB and FoMWof 16.4 fJ/conv-step.

This paper presents a novel adaptive common-mode Cancellation Biopotential Amplifier for portable ECG recording. The amplifier features a converge-free adaptive common-mode cancellation (ACMC) loop with nine MOSFETs, two capacitors, two pseudo resistances and one unity gain buffer. Through periodic detecting and compensating common charge induced by common-mode interference (CMI), ACMC circuit is able to suppressed amplitude of CMI over 100x without requiring a convergence process or additional common-mode references. To verify the design, a prototype is fabricated in 0.18μm CMOS process with a 1.8 V supply. Under power consumption of 16.7μW, measurement results show that 20VPPCMI with a frequency range spanning from 20Hz to 80Hz is suppressed below 200mVPPthat guarantees the normal operation of subsequent instrument amplifier. Also, the input-referred noise (IRN) within 100Hz and common-mode rejection ratio at 50Hz are 1.26μVrmsand 91dB, respectively.

This paper presents a subthreshold-leakage-current-based fully CMOS temperature-to-digital converter with high accuracy and supply rejection. The subthreshold current ratio is constructed by different channel lengths of the same MOSFET type, providing high accuracy and less corner dependence. In addition, the supply sensitivity is enhanced by the proposed subthreshold-leakage-current-based sensing element (SE) and the frequency ratio of two identical currents to frequency converters (CFCs). The prototype was implemented in a 180nm CMOS process. It achieves an inaccuracy of ±0.8°C ($3\sigma$) from 0°C to 100°C after two-point calibration with a resolution of 120mK. Over a wide supply range from 0.8V to 1.6V, the temperature sensor shows a supply sensitivity of 0.9°/V at 30°C. Over the temperature range of 0–100°C, the power supply sensitivity is smaller than 3.4°C/V. Operating at 1V, the sensor has a power consumption of 20nW at 30°C, leading to an FoM of 14.4 pJ$\cdot \text{K}^{2}$.

This article presents a 12-bit column-parallel two-step single-slope analog-to-digital converter (SS ADC). With the merging of analog memory capacitor and input sampling capacitor, the proposed two-step SS ADC realizes simultaneously residue storage and zero-cross detection. The fixed decision point guarantees a static comparator offset. A constant input common-mode level resistor ramp generator, which exploits a current-mode R-2R digital-to-analog converter (DAC) and a variable feedback R-string DAC, is developed to enhance ADC linearity limited by finite common-mode rejection ratio (CMRR) of the operational amplifier. Using a bottom-up foreground self-calibration, harmonic distortion caused by both parasitic capacitor and resistor mismatch is mitigated. This prototype is fabricated using a 130-nm CMOS process. The proposed two-step SS ADC consumes 62-$\mu \text{W}$power when operating at a 100-KS/s sampling frequency and yields a peak spurious-free dynamic range (SFDR) of 76.47 dB with a signal-to-noise-and-distortion ratio (SNDR) of 60.78 dB. The measured differential nonlinearity (DNL) and the integral nonlinearity (INL) are 0.83/−1 and 4.78/−3.31 LSB, respectively.

This article presents a low-power code-recombination (CR) analog-to-digital converter (ADC) with generic feature extraction for wearable electrocardiogram (ECG) sensors in wireless body sensor network (WBSN) applications. The CR ADC features a search forward procedure (SFP) and a search backward procedure (SBP) to hunt for part of the quantization steps cutting down bitcycle and power consumption. Also, CR ADC outputs a digital stream named$K$data served as a compressed feature. A prototyped chip including a proposed ADC is fabricated in a 0.13-$\mu \text{m}$CMOS process. With a 0.6-V supply voltage and a 10-kS/s sampling rate, the measured signal-to-noise-distortion range (SNDR) and spurious-free dynamic range (SFDR) are 58.34 and 70.2 dB, respectively. The ADC consumes only 40-nW power when input residue is within the prediction range defined by ADC’s resolution and the reference voltage, achieving a figure-of-merit (FoM) of 6.2 fJ/conversion-step. The data$K$occupy 2/5 of the raw data and are conducted to categorize cardiovascular diseases illustrating at least 96% accuracy.

This brief presents a second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with two passive integrators. Due to the separation of the preamplifier, these two integrators become independent of each other and the size of the second integrator can be reduced. The NS SAR also realizes the zeros optimization of the noise transfer function (NTF). The analysis shows the NS performance of the proposed ADC is insensitive to the gain variation of the multipath comparator. To mitigate the harmonic distortion caused by capacitor mismatch, thermometer-code 4-bit MSBs are implemented with data weighted averaging (DWA) technique. The overall architecture is simple and robust, which only requires minor modifications to the standard SAR ADC. A prototype 9-bit NS-SAR ADC is designed and simulated in a 130-nm CMOS process. It consumes 59.9 μW of power when operating at 2-MS/s sampling frequency. The proposed ADC achieves peak Schreier figure of merits (FoMs) of 171.9 dB with 78.69-dB signal-to-noise-and-distortion ratio (SNDR) at an oversampling ratio (OSR) of 8.

This paper presents a novel energy efficient code-recombination analog-to-digital converter (ADC) for low power applications. Dynamic tracking algorithm, search forward procedure (SFP) and search backward procedure (SBP) are introduced in this manuscript. Also, to generate the test voltage sequence fed in comparator, a binary code factor (BCF) is presented. And a lookup table (LUT) for digitizing the output code is employed. To verify the algorithm, a 10-bit ADC is designed in 0.13μm CMOS process with a 0.6 V supply. Given a 41.5 Hz sinusoid signal, the proposed ADC exhibits 9.75 effective number of bit (ENOB) and 80.9dB spur-free dynamic range (SFDR) at 10k Hz sample rate. Given full-scale sinusoid signals whose frequency are under 160Hz, the ADC achieves 39-77.4nW power consumption with 2.19-10.8 bitcycles in average, respectively. Also, simulation result shows the DNL and INL is bounded at 0.117 and 0.245LSBs.

This paper proposes a low-power and area efficient 14-bit Successive Approximation Register (SAR) analog-to-digital converter (ADC) for array sensors. A hybrid capacitor digital-to-analog converter (CDAC), which consist of a 10-bit split CDAC and a 5-bit serial CDAC, is utilized to increase the area efficiency. The total required number of unit capacitors are only 52. A foreground digital calibration is employed to compensate the linearity error caused by the capacitor mismatch and bridge parasitic capacitor. The HSPICE post-layout simulation results show that the peak DNL and INL of the proposed ADC are enhanced from 1.27/-1 LSB and 17.29/-16.24 LSB to 0.74/-0.49 LSB and 1.27/-0.54 LSB, respectively. And ENOB is improved from 9.82bit to 13.65 bit at 48.14-KHz input after calibration. With a power consumption of 59 μW, the FOM is 45.42 fJ/step. The CDAC occupies an active area of 15 × 800 μm2and the area efficiency ADC core is only 0.934 μm2/code.