As robots increasingly permeate diverse domains like healthcare, education, service industries and homes, accurately understanding humans’ responses to and behaviour towards robots is crucial. While many human-robot interaction (HRI) studies focus on either quantitative or qualitative approaches, we advocate a mixed-method approach. This study investigated robot norm violations by implementing a scenario where a mobile manipulator robot and a human, in-person, carry out a physical, competitive task. Sixty-two participants were recruited and randomly assigned to either an experimental or a control condition (balanced for age/gender). The scenario was a competitive scavenger hunt game where participants took turns with a robot. We investigated the robot behaviours’ effects on trust, discomfort, competence, enjoyment, participant behaviour and physiological changes. The mixed-method approach integrated physiological measurements, behavioural observations and qualitative responses, thus offering a comprehensive account of HRI dynamics in the context of norm violations. Questionnaire results reveal significant shifts in human perceptions and attitudes when social norms are violated by robots, compared to a norm-compliant control condition. Specifically, trust and enjoyment decrease, discomfort increases and the robot’s perceived competence is compromised. These findings are extended through additional analyses of participants’ physiological changes, behaviours and responses to open-ended questions. Behavioural observations indicated increased verbal engagement and emotional responses, while physiological data showed elevated stress levels in the experimental group. Our study highlights the advantage of a mixed-methods approach combining different qualitative and quantitative data, providing a more comprehensive picture of participants’ perceptions of a robot, and how they react and respond to robot norm violations.

The successful integration of domestic service robots into home environments can bring significant services and convenience to the general population and possibly mitigate important societal issues, such as care provision for older adults. However, home environments are complex, dynamic and object-rich. It is, thus, very probable that service robots will encounter ambiguity while interacting with household items. To enable service robots to be more adaptive, we proposed a learning so-cial referencing computational framework and experimentally evaluated the framework on a mobile manipulator robot, Fetch, in object selection scenarios. The framework allows the robot to (1) detect and analyze the ambiguity level based on the robot's view and user's command, (2) assess the human's attention level and attract their attention, (3) disambiguate references to objects using human feedback and (4) learn novel objects after clarification from the user. System evaluation results are presented. The framework is modular and can be applied to different robotic platforms.

Conditionally automated vehicles provide unique opportunities for drivers to engage in non-driving-related tasks (NDRTs); however, drivers must remain prepared to respond to take-over requests. This paper explores design challenges and potential solutions for supporting reading as an NDRT in SAE Level 3 vehicles. Specifically, we assess two prominent text-presentation techniques: vertical scrolling text presentation (VSTP) and rapid serial visual presentation (RSVP), exploring both in conjunction with their integration with auditory speech displays (ASD). A driving simulation study involving N = 32 participants revealed that RSVP surpassed VSTP in regaining situational awareness, as indicated by lower average braking actuation, and was also preferred by participants. The integration of ASDs with both techniques reduced perceived cognitive workload and improved the user experience, albeit with compromised lateral control. Our findings can help advance the design of human-centered interfaces for reading in conditionally automated vehicles.

Play is valuable in making therapy more enjoyable, and has been studied intensively in human-robot interaction. However, the use of robots as play-mediators in multiplayer games, and the study of the dynamics of players have barely been explored. In this work, pairs of participants played with the MyJay robot in a game with two collaborative conditions (Shared and Fusion). In the Shared condition, participants shared the tasks and in the Fusion condition, participants had to synchronize their commands for the robot. In previous work, we analyzed the video recordings and questionnaires and observed that participants perceived the Fusion condition as more challenging, and requiring more coordination, while the Shared condition was perceived as more enjoyable. This paper will report on new analyses based on physiological and joystick data. The results revealed different patterns of heart rate and usage of the joysticks in the two conditions, while no link between physiological data and enjoyment was found.

This study aimed to investigate the effects of norm-violating behaviour on human perception and attitudes towards robots. Specifically, we examined the impact of a robot performing social norm violations in the context of a competitive scavenger hunt game. During the game, the robot was programmed to engage in predefined behaviours considered as social norm violations, including both injunctive and descriptive norm violations (e.g., cheating, and making loud noises). The study used an experimental and control group, with participants either exposed to norm-violating behaviour or not, respectively. The results indicated that participants in the experimental group had a strong awareness of the norm-violating behaviour according to self-reported assessments. Additionally, post-questionnaire results revealed a significant difference in trust, overall enjoyment, and discomfort between the two groups. These findings show that in our study, participants expected robots to abide by both types of social norms (i.e., injunctive and descriptive) and that violations of them negatively impacted participants’ perceptions and attitudes towards robots. This further emphasizes the importance of considering social norms in the design and programming of robots for human-robot interactions.

Fingertip computing has seen increased interest through miniaturized smart-rings for augmenting digital peripherals. One key advantages of such always-available input devices is the non-necessity to hold a device for interaction, as it remains affixed to a finger for access when needed. Such a wearable device makes it possible to interaction with content even when the hand is encumbered, by grasping or holding objects. Our investigation aims at understanding the properties of this fundamental smart-ring advantage. We designed a smart-ring prototype, ARO (in-Air, on-Ring, on-Object interaction), which facilitates input while grasping objects. To better identify interaction possibilities, we present the results of an elicitation study through which we grouped various forms of micro-gestures possible with ARO while holding objects under different grasp requirements. We then explored the ability for users to perform different navigation tasks (i.e. zooming and panning) using the smart-ring with encumbered hands. In our studies, users were most efficient when using either In-air or On-ring interactions, in comparisons to gestures detected On-object. Furthermore, In-air was the most preferred by our participants. Based on our findings, we conclude with recommendations for the design of future smart-rings and fingertip devices at large, to allow efficient interaction while hands are encumbered.

We explore the design of Hand Proximate User Interfaces (HPUIs) for head-mounted displays (HMDs) to facilitate near-body interactions with the display directly projected on, or around the user's hand. We focus on single-handed input, while taking into consideration the hand anatomy which distorts naturally when the user interacts with the display. Through two user studies, we explore the potential for discrete as well as continuous input. For discrete input, HPUIs favor targets that are directly on the fingers (as opposed to off-finger) as they offer tactile feedback. We demonstrate that continuous interaction is also possible, and is as effective on the fingers as in the off-finger space between the index finger and thumb. We also find that with continuous input, content is more easily controlled when the interaction occurs in the vertical or horizontal axes, and less with diagonal movements. We conclude with applications and recommendations for the design of future HPUIs.

Device that consist of high-speed Analog-to-Digital Converts (ADC) or high-speed interfaces require the input of very low phase noise (below 100 femtoseconds) of reference clock signals. In general, Automatic Test Equipment (ATE) face challenges in measuring certain items. This paper explains reasons why low phase noise clock signals are required for high-speed ADC and discussed the operation concepts and implementation methods of all-digital phase locked-loop (ADPLL). ADPLL exhibits various strengths, with the primary ones being its high precision, high resolution, and jitter cleaner. A conventional testing, precision bench instruments are employed to fulfill the test requirements. By contrast, the integrated testing Automatic Test Equipment platform of V93000 WSPS-PD offers a solution with more satisfactory performance in mass-production testing.

Foldable handheld displays have the potential to offer a rich interaction space, particularly as they fold into a convex form factor, for collocated multi-user interactions. In this paper, we explore Tent mode, a convex configuration of a foldable device partitioned into a primary and a secondary display, as well as a tertiary, Edge display that sits at the intersection of the two. We specifically explore the design space for a wide range of scenarios, such as co-browsing a gallery or co-planning a trip. Through a first collection of interviews, end-users identified a suite of apps that could leverage Tent mode for multi-user interactions. Based on these results we propose an interaction design space that builds on unique Tent mode properties, such as folding, flattening or tilting the device, and the interplay between the three sub-displays. We examine how end-users exploit this rich interaction space when presented with a set of collaborative tasks through a user study, and elicit potential interaction techniques. We implemented these interaction techniques and report on the preliminary user feedback we collected. Finally, we discuss the design implications for collocated interaction in Tent mode configurations.

We present Reality Jockey, a system that confuses the participant's perception of the reality by mixing in a recorded past-reality. The participant will be immersed in a spatialized 3D sound environment that is a mix of sounds from the reality and from the past. The sound environment from the past is augmented with haptic feedback in cross-modality. The haptic feedback is associated with certain sounds such as the vibration in the table when stuff is placed on the table to make the illusion of it happening in live. The seamless transition between live and past creates immersive experience of past events. The blending of live and past allows interactivity. To validate our system, we conducted user studies on 1) does blending live sensations improve such experiences, and 2) how beneficial is it to provide haptic feedbacks in recorded pasts. Potential applications are suggested to illustrate the significance of Reality Jockey.

New media and signal processing applications demand ever higher performance while operating within the tight power constraints of mobile devices. A range of hardware implementations is available to deliver computation with varying degrees of area and power efficiency, from general-purpose processors to application-specific integrated circuits (ASICs). The tradeoff of moving towards more efficient customized solutions such as ASICs is the lack of flexibility in terms of hardware reusability and programmability. In this paper, we propose a customized semi-programmable loop accelerator architecture that exploits the efficiency gains available through high levels of customization, while maintaining sufficient flexibility to execute multiple similar loops. A customized instance of the loop accelerator architecture is generated for a particular loop and then the data and control paths are proactively generalized in an efficient manner to increase flexibility. A compiler mapping phase is then able to map other loops onto the same hardware. The efficiency of the programmable accelerator is compared with non-programmable accelerators and with the OpenRISC 1200 general purpose processor. The programmable accelerator is able to achieve up to 34x better power efficiency and 30x better area efficiency than a simple general purpose processor, while trading off as little as 2x power and area efficiency to the non-programmable accelerator.

Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing the potential for high computation throughput, scalability, low cost, and energy efficiency. CGRAs consist of an array of function units and register files often organized as a two dimensional grid. The most difficult challenge in deploying CGRAs is compiler scheduling technology that can efficiently map software implementations of compute intensive loops onto the array. Traditional schedulers focus on the placement of operations in time and space. With CGRAs, the challenge of placement is compounded by the need to explicitly route operands from producers to consumers. To systematically attack this problem, we take an edge-centric approach to modulo scheduling that focuses on the routing problem as its primary objective. With edge-centric modulo scheduling (EMS), placement is a by-product of the routing process, and the schedule is developed by routing each edge in the dataflow graph. Routing cost metrics provide the scheduler with a global perspective to guide selection. Experiments on a wide variety of compute-intensive loops from the multimedia domain show that EMS improves throughput by 25% over traditional iterative modulo scheduling, and achieves 98% of the throughput of simulated annealing techniques at a fraction of the compilation time.

In the embedded domain, custom hardware in the form of ASICs is often used to implement critical parts of applications when performance and energy efficiency goals cannot be met with software implementations on a general purpose processor or DSP. The downsides of using ASICs include high non-recurring engineering costs, inability to accommodate changes in the application after production, and inability to reuse hardware for new applications. However, by allowing a degree of post-programmability, the hardware can retain high performance and energy efficiency while increasing flexibility and reusability. The difficulty with programmable custom hardware lies in mapping new applications onto an existing datapath that is both sparse and irregular. This paper proposes a constraint-driven modulo scheduler that maps software-pipelineable loops onto programmable loop accelerator hardware. The scheduler is able to target accelerators with widely varying levels of datapath functional capability and connectivity, and thus, varying degrees of programmability. The paper investigates the ability of the scheduler to map new loops onto existing hardware, which depends on both the degree of programmability of the hardware as well as the similarity of the new loop to the original loop for which the hardware was designed.

Hardware accelerators are common in embedded systems that have high performance requirements but must still operate within stringent energy constraints. To facilitate short time-to-market and reduced non-recurring engineering costs, automatic systems that can rapidly generate hardware bearing both power and performance in mind are extremely attractive. This paper proposes the BLADES (Better-than-worst-case Loop Accelerator Design) system for automatically designing self-tuning hardware accelerators that dynamically select their best operating frequency and voltage based on environmental conditions, silicon variation, and input data characteristics. Errors in operation are detected by Razor flip-flops, and recovery is initiated. The architecture efficiently supports detection, rollback, and recovery to provide a highly adaptable and configurable loop accelerator. The overhead of deploying Razor flip-flops is significantly reduced by automatically chaining primitive computation operations together. Results on a range of loop accelerators show average energy savings of 32% gained by voltage scaling below the nominal supply voltage.

Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing the potential for high computation throughput, scalability, low cost and energy efficiency. CGRAs consist of an array of function units and register files generally organized as a two dimensional grid. The most difficult challenge with deploying CGRAs is compiler scheduling technology that can map software implementations of compute intensive loops onto the array. Traditional schedulers are not suitable because they do not take into account the explicit routing of operand values that is necessary. In essence, the problem of binding operations to time slots and resources is extended to also include explicit routing of operands from producers to consumers. To tackle this problem, this paper introduces a software pipelining technique for mapping loop bodies onto CGRAs, referred to as modulo graph embedding. We leverage graph embedding from graph theory, which is used to draw graphs onto a target space. The loop body is essentially drawn onto the CGRA mesh, subject to modulo resource usage constraints. Modulo graph embedding is effective because it can take into account the communication structure of the loop body during mapping. On average, a compute utilization of 56-68% is achieved for a set of loop kernels across three 4x4 CGRA designs.

Scheduling algorithms used in compilers traditionally focus on goals such as reducing schedule length and register pressure or producing compact code. In the context of a hardware synthesis system where the schedule is used to determine various components of the hardware, including datapath, storage, and interconnect, the goals of a scheduler change drastically. In addition to achieving the traditional goals, the scheduler must proactively make decisions to ensure efficient hardware is produced. This paper proposes two exact solutions for cost sensitive modulo scheduling, one based on an integer linear programming formulation and another based on branch-and-bound search. To achieve reasonable compilation times, decomposition techniques to break down the complex scheduling problem into phase ordered sub-problems are proposed. The decomposition techniques work either by partitioning the dataflow graph into smaller subgraphs and optimally scheduling the subgraphs, or by splitting the scheduling problem into two phases, time slot and resource assignment. The effectiveness of cost sensitive modulo scheduling in minimizing the costs of function units, register structures, and interconnection wires are evaluated within a fully automatic synthesis system for loop accelerators. The cost sensitive modulo scheduler increases the efficiency of the resulting hardware significantly compared to both traditional cost unaware and greedy cost aware modulo schedulers.

Application-specific instruction set processors (ASIPs) have the potential to meet the challenging cost, performance, and power goals of future embedded processors by customizing the hardware to suit an application. A central problem is creating compilers that are capable of dealing with the heterogeneous and nonuniform hardware created by the customization process. The processor datapath provides an effective area to customize, but specialized datapaths often have nonuniform connectivity between the function units, making the effective latency of a function unit dependent on the consuming operation. Traditional instruction schedulers break down in this environment due to their locally greedy nature of binding the best choice for a single operation even though that choice may be poor due to a lack of communication paths. To effectively schedule with nonuniform connectivity, we propose a foresighted latency-aware scheduling heuristic (FLASH) that performs lookahead across future scheduling steps to estimate the effects of a potential binding. FLASH combines a set of lookahead heuristics to achieve effective foresight with low compile-time overhead.

Register bypass provides additional datapaths to eliminate data hazards in processor pipelines. The difficulty with register bypass is that the cost of the bypass network is substantial and grows substantially as processor width or pipeline depth are increased. For a single application, many of the bypass paths have extremely low utilization. Thus, there is an important opportunity in the design of application-specific processors to remove a large fraction of the bypass cost while maintaining performance comparable to a processor with full bypass. We propose a systematic design customization process along with a bypass-cognizant compiler scheduler. For the former, we employ iterative design space exploration wherein successive processor designs are selected based on bypass utilization statistics combined with the availability of redundant bypass paths. Compiler scheduling for sparse bypass processors is accomplished by prioritizing function unit choices for each operation prior to scheduling using global information. Results show that for a 5-issue customized VLIW processor, 70% of the bypass cost is eliminated while sacrificing only 10% performance.

Clustered architectures are a solution to the bottleneck of centralized register files in superscalar and VLIW processors. The main challenge associated with clustered architectures is compiler support to effectively partition operations across the available resources on each cluster. In this work, we present a novel technique for clustering operations based on graph partitioning methods. Our approach incorporates new methods of assigning weights to nodes and edges within the dataflow graph to guide the partitioner. Nodes are assigned weights to reflect their resource usage within a cluster, while a slack distribution method intelligently assigns weights to edges to reflect the cost of inserting moves across clusters. A multilevel graph partitioning algorithm, which globally divides a dataflow graph into multiple parts in a hierarchical manner, uses these weights to efficiently generate estimates for the quality of partitions. We found that our algorithm was able to achieve an average of 20% improvement in DSP kernels and 5% improvement in SPECint2000 for a four-cluster architecture.