Demand for miniaturization in deep space proves is increasing due to the need to reduce costs. Along with this trend, transponders, which are essential building blocks for communication, are also required to be downsized. The feasibility of the one-chip transponder with general-purpose low-cost silicon CMOS technology needs to be studied to achieve ultimate downsizing while maintaining electrical reliability. This paper presents a 7.2 GHz CMOS receiver front-end chip with a 65 nm general purpose CMOS process. The direct probing measurements demonstrated that our prototype receiver front-end achieves the input return loss of < -20 dB, the conversion gain of 25 dB, the NF of 2.3 dB, and the IIP3 of -26 dBm, while consumes 20.1mW for the core block including the LNA and the mixers. The measurement results indicate that the receivers of previous deep space transponders can be replaced by a CMOS single chip without sacrificing the functionality and performance.

This paper details the design and implementation of a wide-band, digital-controlledinverter-based phase interpolator (PI) for a spin-wave detection circuit. The PI contains input phase generation part for coarse phase tunning, and PI core part for fine phase tunning. Fabricated using 65nm CMOS technology, the circuit operates across a frequency range of 1GHz to 5GHz with a 1V supply. The chip is implemented in 65nm CMOS technology and operates from 1GHz to 5GHz, with 1V supply. The power consumption of the proposed PI core is 1.89mW at 5GHz. The measured differential non-linearity and integral non-linearity are 0.6 LSB and 5.17 LSB respectively at the worst case.

Automatic test equipment (ATE) for highperformance memory devices needs to transmit and receive ultra-high-speed data/clock waveforms with high fidelity. So far, this has been achieved by applying intricate calibrations with external equipment, which requires significant time, cost, and effort. This paper proposes a method for estimating S-parameters of signal paths to DUT using time-domain reflectometry (TDR), which enables automated calibration for a large number of ATE pins by utilizing built-in drivers and comparators. The proposed method compensates for the effects of reflections from the signal path and the characteristics of the comparator circuit, which affect the TDR measurement results, and enables the accurate prediction of the waveform at the calibration point. Furthermore, without the necessity for external equipment, the proposed method realizes the calibration of a massive number of pins in a short time at a low cost.

This paper presents a power-efficient discrete-time (DT) delta-sigma analog-to-digital converters (ΔΣ ADC) using a correlated level shifting (CLS)-assisted fast self-quenching floating inverter amplifier (FIA) with a sampling noise cancellation (SNC) technique. The CLS technique improves the equivalent open-loop gain of the FIA, while the SNC technique minimizes the sampling noise of the 1st-stage integrator. Compared with the conventional FIAs, the fast self-quenching FIA reduces power consumption while ensuring adequate gain. The prototype of the 2nd-order DT ΔΣ ADC with the proposed FIA is fabricated in a 65-nm CMOS process and achieves fully dynamic operation. It realizes an 88.0dB peak signal-to-noise-and-distortion ratio (SNDR) with an oversampling ratio of 256 for a 19.5kHz bandwidth while consuming 76.2µW from a 1.2V supply at a 10MHz sampling frequency. This ΔΣ ADC achieves 89.6dB dynamic range and 172.1dB SNDR-based Schreier figures of merit.

As phase-locked loop (PLL) architectures become increasingly complex, optimizing the jitter and power performance through calculation alone is becoming more challenging for fractional-N PLLs. To find the most suitable PLL architecture that meets the jitter-power requirements of various applications, a simple and widely-applicable method is in demand to find the optimal jitter-power relation of different PLL architectures. In this paper, we propose the use of a multi-objective evolutionary algorithm (MOEA) to optimize the jitter and power of PLLs, specifically focusing on two popular fractional-N PLL architectures: digital-to-time converter (DTC)-based and harmonic-mixer (HM)-based PLLs. By applying the MOEA, we can achieve optimal jitter and power relationships for both architectures, and the observed trends in jitter and power are explained and supported with calculations.

Root-of-Trust (RoT) uses the hardware primitives to provide security in the integrated electronic systems, preventing attacks against the vital information of the system. The typical hardware primitives are used to generate random numbers and store the system's keys. However, the implementation of these primitives achieves challenges in the system due to the physical phenomena used to obtain the entropy for the random number. On the other hand, the non-volatile memories request special technologies with additional processes and layers. This work presents an implementation of a One-Time Program (OTP) memory using an Anti-Fuse (AF) methodology in 180nm standard CMOS technology. In addition, a Physical Unclonable Function (PUF) is unified, exploiting the post-program current generated in the OTP bit cell. A 128-bit OTP array and high-voltage driver are implemented without any special process and layer, occupying 68000μm2. On the other hand, the PUF implementation achieves 49.02% of uniformity, 49.52% of uniqueness, and 99.88% of reliability in the worst case with Process, Voltage, and Temperature (PVT) variations. In addition, the PUF reports a 2651F2/bit normalized area. The OTP memory application needs 6.7-V to program the AF bit cell.

Dynamic circuit is extensively used where high speed is required such as critical paths in digital and analog/mixed-signal circuits, yet it has not been successfully characterized and integrated into the digital design flows as its characterization is not straightforward due to its complex timing requirement. In this article, we first propose a step-by-step definition of dynamic circuit’s timing parameters required in its timing characterization. We then propose a single ring-oscillator-based test structure for the on-chip measurement of all these defined timing parameters. From the single output of a ring oscillator, this test structure can efficiently extract the timing parameters, including delay and setup/hold times under different conditions of input signal transition time as well as output load capacitance, which is sufficient for the construction of liberty files in the standard-cell library. With the proposed test structure, the setup/hold constraints are examined reiteratively by the ring under actual operating environment. Thus, the worst case result can be obtained and the error rate of the circuit can be estimated.

Stochastic resonance is known as a phenomenon where the signal-to-noise ratio (SNR) of a nonlinear system improves by adding a proper level of noise. To facilitate this phenomenon, this paper proposes a stochastic-resonance analog-to-digital converter (SR ADC) based on a charge-redistribution capacitor digital-to-analog converter (CDAC). The proposed SR ADC utilizes the same architecture as a charge-redistribution successive approximation register (SAR) ADC. In this paper, the performance of the SR ADC is analyzed in detail to demonstrate its feasibility and advantage over the typical Nyquist ADC. The comparison with the SAR ADC in terms of the signal to noise and distortion ratio (SNDR) reveals that the SR ADC is useful to convert the weak input signal whose amplitude is comparable to the input-referred noise of the comparator.

This paper proposes a new method of constructing a compensation filter for the modulated wideband converter (MWC) system. The proposed method can be directly used in the MWC circuit without disconnecting any components. Furthermore, the non-ideal transfer characteristics of the real mixer output and the real ADC input are taken into account in the proposed compensation filter. The proposed method can be utilized in the advanced MWC that enables more flexibility in the design parameters of the MWC. This paper also demonstrates the reconstruction of the Bluetooth signal as a practical example for the evaluation of the reconstruction performance. The MWC successfully reconstructs the time-domain waveform of the signal based on the proposed compensation filter. Even in the case that the total effective number of channels in MWC is small as close to the necessary condition of the MWC, the error vector magnitude (EVM) was still under 1%, which is acceptable for Bluetooth device testing applications.

Fractional-N phase-locked loops using Harmonic-Mixer (HM) based feedback offer good phase noise and spur performance without relying on complex calibration schemes. The HMs in prior art are often realized using the Sample-and-Hold (S/H) operation. This, however, can result in unwanted tones due to intermodulation, which must be suppressed using properly-designed filters. This paper proposes a simple and accurate analysis of the location and magnitude of these tones. We also provide a design guideline for the HM based on this analysis to properly suppress these tones. The results are supported through behavioral and transistor-level simulations.

We propose an all-standard-cell-based synthesizable successive-approximation-register analog-to-digital converter (SAR ADC) which is automatically placed and routed (P&R) using a commercial digital implementation tool. For higher feasibility and wider input range, a differential architecture is proposed with an inverter-based resistive digital-to-analog converter (RDAC) and a four-input comparator. MOSFET gate capacitance is employed for the sampling capacitor. To mitigate its capacitance variation due to input voltage and the leakage between gate and diffusion, we leave the diffusion of the standard cell floating and only use the capacitance between gate and bulk. Two prototypes have been designed in 65-nm bulk CMOS. Prototype I has been fabricated and achieves 10 MS/s, 14.3 mW, and 28.1-dB SNDR in a 6-bit architecture. The performance is improved in Prototype II by proposing a lookup table (LUT)-compensating transistor-configurable inverter-based RDAC and an OR-AND-Inverter (OAI)-based comparator and by employing a thick-oxide diffusion-floating decoupling cell for the sampling capacitor. The default LUT is created during the design phase by a script-controlled automatic simulation routine. The power consumption is significantly reduced as well through improved timing control. Layout-parasitic-extraction (LPE) simulations of Prototype II suggest 35.7- and 47.2-dB SNDRs in 6- and 8-bit versions, respectively. The power consumptions are reduced to 0.91 and 2.52 mW, respectively.

The Modulated Wideband Converter (MWC) is one of the promising sub-Nyquist sampling architectures for sparse wideband signal sensing, cognitive radio applications and so on. In order to design an MWC-based RF receiver that meets a target RF specification, noise figure (NF) of the MWC has to be well-defined by its design properties. This paper reviews a comprehensive explanation for NF of MWC by an analytic approach based on a notation of an average noise figure (ANF) of the MWC, which has been detailed in our prior work in [1]. Consequently, the analysis is proven with simulation and measurement results in order to demonstrate its feasibility.

This paper proposes a time-to-digital converter (TDC) that achieves wide input range and fine time resolution at the same time. The proposed TDC utilizes pulse-shrinking (PS) scheme in the second stage for a fine resolution and two-step (TS) architecture for a wide range. The proposed PS TDC prevents an undesirable nonuniform shrinking rate issue in the conventional PS TDCs by utilizing a built-in offset pulse and an offset pulsewidth detection schemes. With several techniques, including a built-in coarse gain calibration mechanism, the proposed TS architecture overcomes a nonlinearity due to the signal propagation and gain mismatch between coarse and fine stages. The simulation results of the TDC implemented in a 0.18-μm standard CMOS technology demonstrate 2.0-ps resolution and 16-bit range that corresponds to ~130-ns input time interval with 0.08-mm2area. It operates at 3.3 MS/s with 18.0 mW from 1.8-V supply and achieves 1.44-ps single-shot precision.

This paper proposes a synthesizable digital LDO that is implemented with standard-cell-based digital design flow. With inverter chains as voltage-controlled delay lines, the difference between output and reference voltages is converted into delay difference, then compared in time-domain. Since the time-domain difference is straightforwardly captured by a phase detector that consists of a D-FF, the proposed LDO does not need an analog voltage comparator, which requires careful manual design. The prototype of the proposed LDO is fabricated in 65 nm standard CMOS technology with 0.015 mm2area occupation. The measurement results show that with 10.4 MHz internal clock the tracking response to 200 mV switching of the reference voltage is ~4.5 μs and the transient response to 5 mA change of the load current is ~6.6 μs. The quiescent current consumed by the LDO core is as low as 35.2 μA at 10 mA load current, which leads to 99.6 % current efficiency.

A pulse generator (PG) for low power and low duty cycle applications is presented. The PG employs a CMOS switch and a quarter-wavelength transmission line resonator. Since the architecture does not involve feedback gain, the PG is theoretically capable to generate a pulse efficiently at high oscillation frequency (fosc), at which a transistor gain is limited. The PG also features a quick starting time and zero stand-by power. The PG is designed on a 0.18 μm CMOS flipped over a transmission line resonator, implemented by aluminum on a quartz substrate. The prototype consumes 5.4 pJ/pulse, with energy conversion efficiency (ECE) of 2.37% at foscof 11.5 GHz.

This paper proposes a breakdown-pixel-extraction architecture for SPAD sensor. The proposed readout circuit detects the breakdown pixels and their addresses are readout. Therefore, under the faint light environment, this SPAD sensor significantly improves the data readout efficiency. A 15 × 15 SPAD sensor was fabricated in a 0.18 um CMOS process, and a high speed readout is verified by measurement.

Mismatch of power supply integrity between an ATE and a customer board in semiconductor test can lead to test failures such as overkills and underkills. A technique is required to control the power supply impedance of an ATE by feedback control using compensation current injection so that it emulates the impedance of a customer board, eliminating test failures coming from the impedance difference between the two environment. This paper discusses an extension theorem for a multiple power domain with mutual interference, such as a SIMO. Simulation results showed very good agreement between our emulated ATE and the customer board power supply noise waveforms.

This paper proposes a new type of power supply circuit for automatic test equipment (ATE) that has ability to emulate arbitrary power supply impedance. It can emulate power supply impedance of customer environment so as to match the power supply voltage fluctuation waveforms of the ATE and of the customer environment, in order to eliminate overkills/underkills coming from the voltage fluctuation difference caused by the impedance difference between the ATE and a practical operating environment. Our technique adjusts the equivalent impedance by injecting compensation current by a current source attached in parallel with the power supply source. The compensation current is calculated and injected in realtime with a feedback manner based on the power supply voltage measurement with the impedance characteristics of ATE's original power delivery network (PDN) and the customer PDN. Experimental results of prototype circuits are demonstrated to show that the compensation current emulates the impedance, and the both power supply voltage fluctuation waveforms agree well. Limitations and applications of our method are also discussed.

An asynchronous projection and summation circuit is proposed for single photon avalanche diode (SPAD) sensors. Thanks to the efficient interconnection by the asynchronous technique, the circuit can be easily implemented inside 2D SPAD arrays. As a result, the precise summation of the 1b data in one row can be parallel processed for all rows within the same cycle. A test-of-concept chip was fabricated in a 1P5M 0.18 μm CMOS process. By measurement results, the summation of a 15-pixel row can be achieved by the proposed circuit within 22 ns. Such a speed is very important for SPAD-based sensors that need fast summation operations.

Character projection (CP) is a high-speed mask-less exposure technique for electron-beam direct writing (EBDW). In CP exposure of VIA layers, higher throughput is realized if more VIAs are exposed in each EB shot, but it will result in huge number of VIA characters required for arbitrary VIA placement. We adopt one-dimensional VIA array as the basic CP character architecture to increase VIA numbers in an EB shot while saving the stencil area by superposed character arrangement. CP throughput is further improved by layout constraints for VIA placement in detail routing phase. Our experimental results give estimated EB shot counts less than 174G shot/wafer in 14nm technologies.

To improve throughput of Electron Beam Direct Writing (EBDW) with Character Projection (CP) method, we propose a structured routing architecture (SRA) where VIA placement and wire-track interchange is restricted so as to reduce possible layout patterns in VIA and metal layers. CP exposure is accelerated by the increased figure numbers of VIAs and metal segments in each CP character due to the reduced character variations. We demonstrate a design flow that enables routing on the interconnect layer with the limited flexibility using a commercial routing tool and a few own programs. We also present a methodology to design character stencils with improved area efficiency by character superposition. Our experimental results proved the architecture's feasibility in achieving the target EBDW performance in 14nm technologies.

This paper, as a case study and tutorial, discusses testing methods for general PLL features and their operating margin. These methods can be applied all for analog-, digital- and PW-PLLs. There are various kinds of on-chip measurement macros which can be applied for the PLL testing, and for the direction toward digitally assisted analog circuit testing, it is shown that a digitally controlled variable delay and a time to digital converter have a big possibility for PLL testing using only digital signals.

This paper presents an all-digital PMOS and NMOS process variability monitor which utilizes a simple buffer ring with a pulse counter. The proposed circuit monitors the process variability according to a count number of a single pulse which propagates on the buffer ring and a fixed logic level after the pulse vanishes. The proposed circuit has been fabricated in 65nm CMOS process and the measurement results demonstrate that we can monitor the PMOS and NMOS variabilities independently using the proposed monitoring circuit.

This paper proposes an all-digital process variability monitor based on a shared structure of a buffer ring and a ring oscillator. The proposed circuit monitors the PMOS and NMOS process variabilities independently according to a count number of a single pulse which propagates on the ring during the buffer ring mode, and a oscillation frequency during the ring oscillator mode. Using this shared-ring structure, we reduce the occupation area about 40% without loss of process variability monitoring properties compared with the conventional circuit. The proposed shared-ring circuit has been fabricated in 65nm CMOS process and the measurement results with two different wafer lots show the feasibility of the proposed process variability monitoring scheme.

In this paper, we propose an all-digital process variability and aging monitor which utilizes a simple buffer ring with a pulse counter. The proposed circuit monitors the process variability according to a count number of a single pulse which propagates on the buffer ring and a fixed logic level after the pulse vanishes. Using the proposed circuit in combination with a simple ring oscillator which monitors its oscillation period, we can calculate the rise and fall delay values and can monitors the variabilities of PMOS and NMOS devices independently. The experimental results of the circuit simulation on 65nm CMOS process indicate the feasibility of the proposed monitoring circuit. The proposed monitoring technique is suitable not only for the on-chip process variability monitoring but also for the infield monitoring of aging effects such as negative bias instability (NBTI) and channel hot carrier (CHC).

This paper proposes a yield optimization method for standard cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield enhanced standard cells and the proposed method automatically creates yield enhanced cell layouts by decompacting the original cell layout using linear programming. We develop a novel accurate linear delay model which approximates the difference from the original delay and use this model to formulate the timing constraints into linear programming. Experimental results show that the proposed method can pick up the yield variants of a cell layout from the tradeoff curve of cell delay versus critical area and is used to create the yield enhanced cell library which is essential to realize yield-aware VLSI design flows.

This paper proposes a yield optimization method for standard-cells under timing constraints. Yield-aware logic synthesis and physical optimization require yield-enhanced standard cells and the proposed method automatically creates yield-enhanced cell layouts by de-compacting the original cell layout. However, the careless modification of the original layout may degrade its performances severely. Therefore, the proposed method de-compacts the original layout under given timing constraints using a linear programming (LP). We develop a new accurate linear delay model which approximates the difference from the original delay and use this model to formulate the timing constraints in the LP. Experimental results show that the proposed method can pick up the yield variants of a cell layout from the trade off curve of cell delay versus critical area and is used to create the yield-enhanced cell library which is essential to realize yield-aware VLSI design flows

This paper proposes a minimum-width multi-row transistor placement method for CMOS cells in presence of non-dual P and N type transistors. This is the first exact multi-row transistor placement method which can be applied to CMOS cells with any types of structure. Non-dual CMOS cells occupy a major part of an industrial standard-cell library. To generate the exact minimum-width transistor placement of non-dual CMOS cells, we formulate the transistor placement problem into Boolean satisfiability (SAT) problem considering the P and N type transistors individually. Using the proposed method, the transistor placement problem of any types of CMOS cells can be solved exactly. Moreover, the proposed method uses more efficient gate connection style, and generates more area-efficient transistor placements than the conventional method. Experimental results show that the proposed method can generate the minimum width multi-row transistor placement of the cells with up to 26 transistors in reasonable time

This paper proposes flat and hierarchical approaches for generating a minimum-width transistor placement of CMOS cells in presence of non-dual P and N type transistors. Our approaches are the first exact method which can be applied to CMOS cells with any types of structure. We formulate the transistor placement problem into Boolean Satisfiability (SAT) problem considering the P and N type transistors individually. The experimental results show that our flat approach generates smaller width placement for 29 out of 103 dual cells than that of the conventional method, and the width of only 3 out of 147 cells solved by our hierarchical approach are larger than that of the flat approach. Using the hierarchical approach, 81% of 340 cells in an industrial standard-cell library of 90 nm technology are solved within one hour for each cell, whereas 32% using the conventional exact method.

Application-specific integrated circuits (ASICs) with high-performance embedded memory array with suitable design route have considerable merits in terms of system speed, scalability with technology and system cost. The choice of design approach according to applications is critical. For highly memory-rich applications, one of the recently developed memory ASICs, an integrated cache memory is described. Another example suited for large-size random logic and high-density memory is a structure array approach. A recently developed 72 K track-free gate array with 1 Mb DRAM is described.>