Larger cache sizes closer to processor cores increase processing efficiency, but physical limitations restrict cache sizes at a given latency. Effective cache capacity can be expanded via the inline compression of data as it enters a lower level cache. Using the IBM Telum®processor cache hierarchy as a comparative baseline, this paper presents a custom compression scheme designed for small, line-sized data blocks, examines op-timal compressor/decompressor placement, solutions to common compression drawbacks, and proposes a tiered design blueprint to facilitate product integration. The impact of compression and prediction-assisted adaptive compression on effective cache capacity, hit rate and access latency across several typical industry workloads is explored.

Making software dependable is one of most important aspects in safety-critical system such as a nuclear power plant. Dependable programming techniques to get rid of undependable properties, such as ambiguity, wrong uses of elements, discordance, etc., help engineers reduce the faults in programs. This paper proposes the practice guidelines for function block diagram (FBD) which is a programming language for programmable logic controllers (PLC) widely used in industry. The guidelines show that what cases cause undependable properties and how the properties should be eliminated to be dependable ones in FBD programs. The paper introduces the application of guidelines to the trip (shutdown) logic of bistable processor (BP) in reactor protection system (RPS) developed in the Korea Nuclear Instrumentation and Control System R&D Center (KNICS). The application describes that the guidelines eliminates undependable properties in the trip logic.

SUMMARY Automated and effective testing for function block diagram (FBD) programs has become an important issue, as FBD is increasingly used in implementing safety‐critical systems. This work describes an automated test case generation technique for FBD programs and its associated tool—FBDTester. Given an FBD program and desired test coverage criteria, FBDTester generates test requirements and invokes the Satisfiability Modulo Theories solver iteratively to derive a set of test cases. An industrial case study using reactor protection system software shows that the automatically generated test suites detected at least 82% of the known faults, whereas manually generated test cases only detected approximately 35%. Mutation analysis revealed that the automatically generated test suites substantially outperformed manually generated ones. Although test sequence generation requires some manual effort in the current FBDTester, it is apparent that the proposed approach significantly improves the efficiency and the reliability of FBD testing. Copyright © 2014 John Wiley & Sons, Ltd.

This research is to design a simple but high performance TLB (translation lookaside buffer) system with low power consumption. Thus, we propose a new TLB structure supporting two page sizes dynamically and selectively for high performance and low cost design without any operating system support. For high performance, a promotion-TLB is designed by supporting two page sizes. Also in order to attain low power consumption, a banked-TLB is constructed by dividing one fully associative TLB space into two sub fully associative TLBs. These two structures are integrated to form a banked-promotion TLB as a low power and high performance TLB structure for embedded processors. According to the results of comparison and analysis, a similar performance can be achieved by using fewer TLB entries and also energy dissipation can be reduced by around 50% compared with the fully associative TLB.

This paper proposes a new cache system that can increase the effect by temporal and spatial locality by using only simple hardware control without any locality detection hardware or compiler aid. The proposed cache system consists of two caches with different associativities and different block sizes, i.e., a direct-mapped cache with small block size and a fully associative spatial buffer with large block size as a multiple of small blocks. Therefore, the spatial locality can be exploited by aggressively fetching large blocks including any missed small block into the buffer, and the temporal locality can also be exploited by selectively storing small blocks that were referenced at the spatial buffer in the past. To determine the blocks to be stored at the direct-mapped cache, the proposed cache system uses a time interval-based selection mechanism. According to the simulation results, similar performance can be achieved by using four times smaller cache size compared with the conventional direct-mapped cache.

This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compressed form. However, the decompression time causes a critical effect on the memory access time and variable-sized compressed blocks tend to increase the design complexity of the compressed cache architecture. This paper suggests several techniques to reduce the decompression overhead and to manage the compressed blocks efficiently which include selective compression, fixed space allocation for the compressed blocks, parallel decompression, the use of a decompression buffer, and so on. Moreover a simple compressed cache architecture based on the above techniques and its management method are proposed. The results from trace-driven simulation show that this approach can provide around 35% decrease in the on-chip cache miss ratio as well as a 53% decrease in the data traffic over the conventional memory systems. Also, a large amount of the decompression overhead can be reduced, and thus the average memory access time can also be reduced by maximum 20% against the conventional memory systems.