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R. Téllez-Girón

dblp:28/3817 · DBLP profile ↗
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2ranked-venue papers
1as first author
0since 2021 · last 1987
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 50% Hardware reliability and fault tolerance · 50%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware reliability and fault tolerance
error latency		 0.011979
Comments on "The Error Latency of a Fault in a Sequential Digital Circuit" · IEEE Trans. Computers 1979
Electronic design automation
hardware verification and test		 0.011979
Comments on "The Error Latency of a Fault in a Sequential Digital Circuit" · IEEE Trans. Computers 1979

Methods — techniques the papers use, named apart from their topics

approximation method · 0.0
YearPublicationVenuePosition
1987 A combined testing approach for instruction-set-based data processing devices
R. Téllez-Girón, K. Ergang, Axel Hunger
 Microprocessing and Microprogramming1
1979 Comments on "The Error Latency of a Fault in a Sequential Digital Circuit"
abstract
In the paper "The Error Latency of a Fault in a Sequential Digital Circuit," the method presented in [1] to evaluate the random test length to be applied to a sequential circuit, is called the "approximation method." We agree with this name, but wish to offer the following interpretations and clarifications (using the notations of Shedletsky and McCluskey1).
R. David, R. Téllez-Girón
 IEEE Trans. Computers2