The determination of transcriptome profiles that mediate immune therapy in cancer remains a major clinical and biological challenge. Despite responses induced by immune-check points inhibitors (ICIs) in diverse tumor types and all the big breakthroughs in cancer immunotherapy, most patients with solid tumors do not respond to ICI therapies. It still remains a big challenge to predict the ICI treatment response. Here, we propose a framework with multiple prior knowledge networks guided for immune checkpoints inhibitors prediction-DeepOmix-ICI (or ICInet for short). ICInet can predict the immune therapy response by leveraging geometric deep learning and prior biological knowledge graphs of gene-gene interactions. Here, we demonstrate more than 600 ICI-treated patients with ICI response data and gene expression profile to apply on ICInet. ICInet was used for ICI therapy responses prediciton across different cancer types-melanoma, gastric cancer and bladder cancer, which includes 7 cohorts from different data sources. ICInet is able to robustly generalize into multiple cancer types. Moreover, the performance of ICInet in those cancer types can outperform other ICI biomarkers in the clinic. Our model [area under the curve (AUC = 0.85)] generally outperformed other measures, including tumor mutational burden (AUC = 0.62) and programmed cell death ligand-1 score (AUC = 0.74). Therefore, our study presents a prior-knowledge guided deep learning method to effectively select immunotherapy-response-associated biomarkers, thereby improving the prediction of immunotherapy response for precision oncology.

This article consists only of a collection of slides from the author's conference presentation.

The open source RISC-V ISA has been quickly gaining momentum. This paper presents Xuantie-910, an industry leading 64-bit high performance embedded RISC-V processor from Alibaba T-Head division. It is fully based on the RV64GCV instruction set and it features custom extensions to arithmetic operation, bit manipulation, load and store, TLB and cache operations. It also implements the 0.7.1 stable release of RISCV vector extension specification for high efficiency vector processing. Xuantie-910 supports multi-core multi-cluster SMP with cache coherence. Each cluster contains 1 to 4 core(s) capable of booting the Linux operating system. Each single core utilizes the state-of-the-art 12-stage deep pipeline, out-of-order, multi-issue superscalar architecture, achieving a maximum clock frequency of 2.5 GHz in the typical process, voltage and temperature condition in a TSMC 12nm FinFET process technology. Each single core with the vector execution unit costs an area of 0.8 mm2, (excluding the L2 cache). The toolchain is enhanced significantly to support the vector extension and custom extensions. Through hardware and toolchain co-optimization, to date Xuantie-910 delivers the highest performance (in terms of IPC, speed, and power efficiency) for a number of industrial control flow and data computing benchmarks, when compared with its predecessors in the RISC-V family. Xuantie-910 FPGA implementation has been deployed in the data centers of Alibaba Cloud, for applicationspecific acceleration (e.g., blockchain transaction). The ASIC deployment at low-cost SoC applications, such as IoT endpoints and edge computing, is planned to facilitate Alibaba’s end-to-end and cloud-to-edge computing infrastructure.

Process variations have become a serious concern for nanometer technologies. The interconnect and device variations include inter-and intra-die variations of geometries, as well as process and electrical parameters. In this paper, pattern (i.e. density, width and space) dependent interconnect thickness and width variations are studied based on a well-designed test chip in a 90 nm technology. The parasitic resistance and capacitance variations due to the process variations are investigated, and process-variation-aware extraction techniques are proposed. In the test chip, electrical and physical measurements show strong metal thickness and width variations mainly due to chemical mechanical polishing (CMP) in nanometer technologies. The loop inductance dependence of return patterns is also validated in the test chip. The proposed new characterization methods extract interconnect RC variations as a function of metal density, width and space. Simulation results show excellent agreement between on-wafer measurements and extractions of various RC structures, including a set of metal loaded/unloaded ring oscillators in a complex wiring environment.

Modeling on-chip inductive effects for interconnects of multi-gigahertz microprocessors remains challenging. SPICE simulation of these effects is very slow because of the large number of mutual inductances. Meanwhile, ignoring the non-linear behavior of drivers in a fast linear circuit simulator results in large errors for the inductive effect. In this paper, a fast and accurate time-domain transient analysis approach is presented, which captures the non-linearity of circuit drivers, the effect of non-ideal ground and de-coupling capacitors in a bus structure. The proposed method models the non-linearity of drivers in conjunction with specific bus geometries. Linearized waveforms at each driver output are incorporated into an interconnect reduced-order simulator for fast transient simulation. In addition, non-ideal ground and de-coupling capacitor models enable accurate signal and ground bounce simulations. Results show that this simulation approach is up-to 68x faster than SPICE while maintaining 95% accuracy.