An analog test bus and serial digital access to ADC and DAC parallel ports are two widely used analog DFT techniques. Unfortunately, they cannot be described in a standard way that could facilitate automatic test pattern generation (ATPG). Furthermore, serially accessing an ADC/DAC is typically too inefficient for periodic sampling for various reasons, but mostly because of the capture/update-then-shift sequence used in IEEE 1149.1, 1500, and 1687. This paper shows that if a small amount of digital circuitry is added to each accessed ADC/DAC parallel port, they could be described in IEEE 1687 instrument connection language (ICL) to facilitate optimally efficient streaming access to the parallel ports. Furthermore, this could be automated by adding our proposed “iStream” as a new 1687 procedural description language (PDL) command. We provide examples of how it would be used, along with evidence to show it can provide more efficient (up to 2X, or more) serial access rate to ADCs and DACs than previous automatable approaches.

Achieving automotive quality requires IC tests that achieve 100% coverage of potential defects. With new cell-aware digital test pattern generation techniques and the simple stuck-at fault model, this has proven practical for digital circuitry, but there is no equivalent for mixed-signal circuitry. A simple but realistic analog defect model is described, based on industrial observations and theory. It is consistent with previous proposals, but has novel differences that make it suitable for schematic and layout-extracted netlists and more efficient to simulate. A couple of examples show its effectiveness.

Multi-site testing is generally regarded as the most-effective way to reduce the cost of test. Testing two devices on an ATE at the same time is half the cost of testing only one, but only if the ATE does not need twice as many channels. It is general practice in industry to use reduced pin-count test (RPCT) access to facilitate testing more ICs in parallel, as well as testing high pin-count ICs on low channel-count testers. This session will address how quality is maintained for the I/Os that are not accessed by ATE channels, advantages of RPCT beyond cost reduction, disadvantages of RPCT, yield impact, differences between RPCT for wafer-sort and final test, DFT for RPCT, handling mixed-signal functions, and ultimately, the smallest number of signal pins that can be accessed for thoroughly testing an IC.

Testing the quality of the interposer wires in a 2.5-D stacked IC can avoid the penalty arising from bonding known-good dies to a defective interposer. However, an interposer is particularly hard to test alone due to the lack of a device layer. This paper addresses this problem by proposing amid-bond test method - in which the interposer is tested after each die is attached to the substrate. We borrow the technique of pre-bond test method for the TSV and enhance it by a length-normalization scheme to cope with interposer wires of diverse wire lengths. Simulations show that this mid-bond test method can catch a high percentage of open faults before subsequent dies are attached.

Testing the quality of prebond through-silicon vias (TSV) is a vital part of the Known-Good-Die test that is often necessary to retain a high compound yield for 3-D stacked integrated circuits. In this paper, we present a versatile prebond TSV test method applicable before wafer thinning when the deep end of the TSV is inaccessible as buried in the still-thick wafer. Technical merits include: 1) the ability to handle both the resistive open fault and the leakage fault in the same test structure; 2) a capability that allows an user to have a better measure of the severity of the fault; and 3) an all-digital and easy to implement design-for-testability circuit.

A parametric delay fault could arise in a through-silicon via (TSV) of a 3-D IC due to a manufacturing defect. Identification of such a fault is essential for fault diagnosis, yield-learning, and/or reliability screening. In this paper, we present an innovative design-for-testability technique called variable output thresholding. We discovered that by dynamically switching the output of a TSV from a normal inverter to a Schmitt-Trigger inverter, the parametric delay fault on the TSV can be characterized and detected. SPICE simulation reveals that this technique remains effective even when there is significant process variation. A scalable test infrastructure indicates that the test time is modest at only 17.2 ms for 1024 TSVs and 648.8 ms for 32768 TSVs when the test clock is running at 10 MHz.

In this work, we present a robust small delay test scheme for through-silicon vias (TSVs) in a 3D IC. By changing the output inverter's threshold of a TSV in a testable oscillation ring structure, we can approximate the propagation delay across that TSV, and thereby detecting a small delay fault. SPICE simulation reveals that this Variable Output Thresholding (VOT) technique is still effective even when there is significant process variation in detecting a slow TSV with some resistive open defect that may escape the traditional at-speed test.

A TSV in a 3D IC could suffer from two major types of parametric faults — a resistive open fault, or a leakage fault. Dealing with these parametric faults (which do not destroy the functionality of a TSV completely but only degrade its quality or performance) is often trickier than dealing with a stuck-at fault. Previous works have not proposed a unified test structure and method that can characterize their respective effects. Based on our previous test structure, called VOT (Variable Output Threshold) scheme for delay faults, we propose a unified in-situ characterization flow for both parametric fault types of a post-bond TSV. With this flow, one can easily derive a more insightful assessment of a parametric fault in production test, process monitoring, and/or diagnosis-driven yield learning.

This paper describes a test bus suitable for conveying analog and digital signals to/from an unlimited number of circuit nodes with almost unlimited time or voltage resolution, in contrast to analog buses which are unlimited only in voltage resolution. A strategy is described that extends a silicon-proven approach for BIST of jitter and delays in PLLs, to BIST of 'random' analog functions. A variety of stimulus and response capture approaches is used to translate analog parameters from any number of circuit nodes, addressed by a P1687-like scheme, into digital waveforms conveyed via digitally under sampled serial bit streams or analog over sampled sigma-delta bit streams, to shared RTL-synthesized measurement circuits. Examples are presented for diverse circuit parameters.

An I/O BIST with calibrated 50 ps delay measurement resolution, presented at ITC'10, requires no changes to 1149.1 boundary scan cells nor the I/O cells they access, and avoids using delay cells or delay matching. In this paper, we describe how we improved the silicon-proven resolution by 10X (to 5 ps) without limiting the delay range. The finer resolution enables measurement of crosstalk between I/Os, which is a known source of jitter - we provide results measured on an FPGA. We also describe three new tests (for duty cycle, slew rate, and skew) that unobtrusively test I/O parameters while high-speed data from core logic is being transmitted on DDR pins (or USB2). Lastly, we describe how adaptive test limits are applied by setting limits on-chip relative to the average value measured for any selected group of pins on each device.

PLLs generate clocks for the core logic in many ICs. As frequencies increase above 500 MHz, jitter and duty cycle error become significant and more likely to affect logic function. Measuring these parameters off-chip can be too expensive or impractical. This paper describes how a PLL BIST is being implemented in production ICs to test jitter, duty cycle, phase delay, frequency ratio, and lock time. It discusses some of the implementation problems and lessons, and how characterization was performed using a PC with graphical test generation software and off-the-shelf reference clock sources to produce production test patterns. Results for a test chip are included, demonstrating that calibrated, picosecond-precision measurements are now practical for production test.

To minimize test costs for ASICs and boards, many manufacturers use reduced pin-count access and/or boundary scan-based test. Only DC parameters and basic connectivity are tested, because it takes too much engineering effort to test AC performance. This paper describes a BIST circuit that facilitates testing AC performance of I/O pins via standard boundary scan, without modifying or contacting the I/O circuitry. Process-insensitive, RTL-synthesized BIST circuitry is added outside the TAP controller. It uses a system clock and an asynchronous clock generated by a PLL in the IC to control the update and capture timing of the boundary scan cells. Silicon results show that with a typical PLL, I/O delays can be measured with adjustable precision ranging from 5 ns to 50 ps, and measurements can be compared to per-pin test limits on-chip. This permits automated test generation for I/O pin AC (and DC) parameters, and any connected board-level components, and facilitates more multi-site IC testing.

As printed circuit board dimensions continue to decrease, in-circuit tester (ICT) access using a bed-of-nails plus capacitive sensing is increasingly difficult. Stimulus injection using IEEE 1149.1 boundary-scan has been proposed as an alternative, but without modification it has significant limitations. An IEEE-supported Working Group is developing an extension entitled, ¿1149.8.1 - Draft standard for boundary-scan-based stimulus of interconnects to passive and/or active components¿. It would add capabilities to 1149.1 that facilitate testing of connections to non-boundary-scan components, especially passive components and vacant connectors that are connected to devices equipped with 1149.8.1 facilities. This paper describes existing limitations, IC design changes that would address them, some experimental results, and a summary of how this proposed standard is evolving.

PLLs are the heart of most SoCs, so their performance affects many tests. Practical, published PLL BIST approaches cannot measure1 GHz. This paper describes how a SerDes undersampling DFT technique was adapted to test multiple PLLs and DLLs for jitter, output frequency, duty cycle, and other parameters. Its multi-GHz range, sub-picosecond jitter noise floor, and minimal silicon area are better than for any previous silicon-proven DFT or BIST that needs no calibration or analog circuitry. FPGA implementation results are provided.

A built-off self-test (BOST) approach is described in which a self-testing FPGA on a device-under-test (DUT) interface board can test serializers or deserializers at serial rates up to 6.4 Gbps, and some SerDes at much higher rates. With a few on-chip undersampling latches, the same BOST can also test embedded PLLs, DLLs, clocks, and logic delays. For SerDes functions, the structurally tested parameters include jitter and its constituent components, jitter tolerance, and waveshape. For other embedded functions, the tested parameters include jitter, duty cycle, frequency, phase error, and delay. The hardware results show that picosecond resolution has been achieved, with minimal or no changes to the DUT.

A suite of structural tests is described that uses on-chip under sampling to measure parameters that affect jitter tolerance in a multi-gigabit-per-second (Gbps) receiver. The tests measure high-frequency jitter (RMS value and histogram) in the received signal and in the recovered clock, plus transition-density dependent phase-shift, mean sampling position in the signal eye, sampling clock phase error, and pin-to-pin skew, all with near-picosecond resolution and repeatability, in tens of milliseconds. Hardware results for a 3 Gbps serializer/deserializer (SerDes) IC are included. The new method is suitable for an unlimited number of channels, it simplifies test hardware, it reduces production test time, and is suitable for any tester. The diagnostic capabilities facilitate improving yield and quality

In conclusion, correct-by-construction design must be augmented with design-for-test that permits diagnostic, parametric, production tests so that parametric margin can be continuously monitored during production and in the end application. Otherwise, "correct-by-construction" devices are guaranteed to fail at the most inconvenient time

A suite of structural tests is described that uses on-chip under sampling to measure parameters that affect jitter tolerance in a multi-gigabit-per-second (Gbps) receiver. The tests measure high-frequency jitter (RMS value and histogram) in the received signal and in the recovered clock, plus transition-density dependent phase-shift, mean sampling position in the signal eye, sampling clock phase error, and pin-to-pin skew, all with near-picosecond resolution and repeatability, in tens of milliseconds. Hardware results for a 3 Gbps serializer/ deserializer (SerDes) IC are included. The new method is suitable for an unlimited number of channels, it simplifies test hardware, it reduces production test time, and is suitable for any tester. The diagnostic capabilities facilitate improving yield and quality

Single board, and now multi-board testability is highly conditioned by the availability of various forms of boundary scan technology. This paper surveys the three more recent IEEE Standards relating to boundary scan. The paper is based on three backgrounders prepared by members of the individual Working Groups for the IEEE Standards booth at ITC 2003.

Gigahertz serialization and deserialization (SERDES) has become a dominant inter-chip and inter-board data transmission technique. Signal integrity is the primary factor determining its bit error rate, typically less than 10/sup -12/, so the primary production test challenges are testing picosecond jitter and the signal eye opening. Off-chip jitter and rise/fall time measurements are limited by hardware complexity, access, bandwidth, and noise. Published on-chip measurement techniques are limited by delay line jitter. This paper presents a new jitter test technique that has been demonstrated on an FPGA to achieve less than 1 ps RMS self-jitter, and a new signal eye test that has unlimited bandwidth; neither test uses high speed circuitry. The all-digital technique uses the receiver itself to demodulate the signal jitter to a low-speed bit stream that is analyzed by a single-clock domain, synthesizable circuit. This is combined with logic BIST and 1149.6 boundary scan to completely test an IC.

As the sampling frequency of new ADCs and DACs increases, it gets more dificult to accurately convey the analog stimulus or response to or from the converter under test - there is a bandwidth bottleneck. This paper describes a technique that uses a 400 kHz analog bus, such as the standard 1149.4 bus, to convey an arbitrary analog signal, and converts the signal to or from a high frequency at the converter, on-chip. This permits existing low-frequency distortion tests, both ATEbased and embedded, to be used for high frequency converters. High frequency noise is easily filtered out, permitting a more repeatable test and the use of low cost testers. A hypothetical 100 MHz, 14-bit ADC and DAC are used as examples. The technique has reduced sensitivity to sampling jitter, and 16-18 bit linearity appears feasible.

A novel approach is presented for digital generation of an analog waveform suitable for BIST of high-resolution analog-to-digital converters (ADCs). The staircase-like exponential waveform is shown to have properties of a perfectly linear ramp when used as the stimulus for a 3rd order polynomial fitting algorithm that measures offset, gain, 2nd and 3rd harmonic distortion. The technique is particularly suitable for testing high resolution (>12 bits) sigma-delta ADCs in a noisy environment, which can then be used to test digital-to-analog converters (DACs). Experimental results for a 44 kHz 16-bit ADC show that the technique measures distortion with better than 0.01% accuracy in the presence of random and 50 or 60 Hz noise.

Summary form only given. BIST, by definition, requires on-chip generation of the stimulus, and on-chip analysis of the response, sufficient to produce a pass/fail result or a series of bits that any tester can compare bit-wise to the expected bit values. Many so-called on-chip mixed-signal built-in self-test (MS-BIST) approaches in fact require the ATE to supply the stimulus (analog waveform, or sigma-delta bit stream), or perform some response analysis (DSP, histogram processing, or RMS calculation), especially when >10 bits linearity is being tested. For MS-BIST to be technically and economically successful, it must test all key parameters, at-speed, in a test time comparable to that of mixed-signal ATE, with less than 1-2K gates, and permit new types of tests (and higher accuracy tests) to be added post-silicon -presently this is only available in fiction. For MS-BIST to become fact, it will have to evolve gracefully and gradually from partitioned test resources. New DFT and test methods that minimize on-chip circuitry will be implemented first, and then the on-chip portion will increase as each component of the test circuitry and method is proven in production.

Embedded test of memory and random logic can enable very low cost ATE to test large, high speed ICs because high quality at-speed tests can be generated onchip. However, it is also necessary to test the DC and AC parameters of the input/output (I/O) circuitry. This paper describes how most I/O pin characteristics can be tested cost-effectively with a variety of novel techniques that exploit the 1149.1 and 1149.4 test standards. The techniques measure VOL/IOL, VOH/IOH, VIH, and VIL at DC, perform at-speed I/O wrap, and test on-chip power rail impedance, all via minimum pin-count (MPC) access. The 1149.4 bus is also suitable, of course, for testing mixed-signal functions. The paper then discusses costs and benefits of MPC testing of high pin-count ICs on a low cost tester to show that testing costs can be reduced to insignificance.

This paper describes a general purpose IC intended for improving the testability of mixed-signal circuit boards and for investigating enhancements to the IEEE 1149.4 mixed-signal test bus. The 20-pin IC makes it possible to measure the impedance of 9 board-level circuit nodes via a 2-wire analog bus, and to monitor high frequency signals (HF>10 MHz) in continuous or sampled time. The IC design, performance trade-offs, and measured performance are discussed. Impedance measurement accuracy (/spl plusmn/5 ohms for first samples) was shown to be limited primarily by function pin series resistance R/sub COM/; a simple technique for measuring its value is described. Lastly, results for a demonstration circuit board, and software available from many vendors, are presented.

Testing for IC pin leakage current is important because it detects many subtle I/O circuitry faults. A technique is introduced in which the leakage current of pins is tested (or measured) during wafer probing using existing 1149.1 boundary scan access only - the tested pins are not contacted The technique requires every tested pad to have a tristate driver and receiver ("I/O wrap"), and relies on knowing approximately each pad's capacitance and each receiver's switching point voltage. Experimental results for a 500 signal-pin IC, that also contained an embedded test for the logic, show that the test program is simplified and runs on a very low cost tester in a reduced test time, while overall yield is maintained or improved.

Phase-locked loops (PLLs) are an essential building block of most digital and mixed-signal ICs. This paper describes a built-in self-test (BIST) circuit that tests the key analog parameters of PLLs, using only logic gates that can be synthesized from a hardware description language (HDL). The parameters tested include lock range, lock time, RMS jitter, and loop gain (from which the natural frequency is calculated). Experimental waveforms and results are shown for a 200 MHz PLL which uses a phase-frequency detector. Test time is typically 10 ms, much faster than for conventional testing.

This paper first summarizes the complete range of analog defects and resultant faults. A complete set of metrics is then derived for measuring the quality of analog tests. The probability-based equations for fault coverage, defect level, yield coverage, and yield loss are self-consistent, and consistent with existing equations for digital test metrics. We introduce the concept of partial coverage, show that it is inherent to analog testing, and show that coverage cannot be calculated without knowing the performance specifications for a circuit, as well as the process parameter distributions. Practical methods for calculating probabilities are discussed, and simple, illustrative examples given.

Ask ASIC designers whether they plan to use BIST, and the answer will depend on whether the designer has seen the 'swamp' of test complexity for deep submicron ICs. With gate counts >500 K and internal clock rates >200 MHz, test costs can equal silicon costs unless embedded test facilities are used. For these ICs, which are quickly becoming mainstream, which functions are best tested with BIST? An attempt is made to answer this question, and it is concluded that, compared to external ATE, BIST can be more effective for testing multiple embedded memories, high speed random logic, and some mixed-signal functions. It is recommended that designers and test engineers should anticipate the approaching swamp of test complexity and decreasing test yields.

The issue of whether the proposed P1149.4 Standard for a Mixed-Signal Test Bus will be a net benefit to board level design and test seems to be more or less settled: for the extremely dense circuit boards which will be commonplace in five years, and in today's multi-chip modules, P1149.4 offers a solution where no other exists. P1149.4 was aimed at solving test issues for these mixed-signal boards. For boards which do not have test access issues, P1149.4 may not be worth its costs. So the key question about the proposed P1149.4 Standard is whether it will be a net benefit for IC designers, without considering the system-level benefits.

An accurate and simple method is introduced for determining the third order polynomial that best fits a set of data points containing random noise. The coefficients of the polynomial are translated into offset, gain, and harmonic distortion for an analog-to-digital converter (ADC) driven by a digital-to-analog converter (DAC) or other appropriate signal source. The algorithm is efficient enough to be implemented as a built-in self-test for an IC, and is particularly suitable for sigma-delta converters.

This paper treats the problem of testing integrated operational amplifiers. The efficiency of a new low-cost vector-less test solution, known as oscillation-test, is investigated. During the test mode, the op-amps are converted to a circuit that oscillates. The oscillation frequency is evaluated to monitor faults. The tolerance band of the oscillation frequency is determined using a Monte Carlo analysis taking into account the nominal tolerance of all important technology and design parameters. Faults in the op-amps under test which cause the oscillation frequency to exit the tolerance band can therefore be detected. Some design for testability (DFT) rules to rearrange op-amps to form oscillators are presented and the related practical problems and limitations are discussed. The oscillation frequency can be easily and precisely evaluated using pure digital circuitry. The simulation and practical implementation results confirm that the presented method assures a high fault coverage with a low area overhead.

This paper summarizes key elements of the proposed IEEE P1149.4 Mixed-Signal Test Bus Standard, examines costs and benefits in detail, and includes specific circuit examples. The significant costs are silicon area and pins. Benefits include test cost reduction, diagnosability, and unique capabilities. Changes proposed since ITC'93 and areas of controversy are noted for this un-released standard.

This paper describes an on-chip analog bus whose bandwidth is limited primarily by an off-chip amplifier. It uses only a digital 3-state inverter for each bus input. The high-speed and constant low-input capacitance of this scheme make it suitable for measuring sensitive or even digital signals. For equal silicon area, the signal bandwidth is demonstrated to be 10 to 40 times that of previously reported transmission gate schemes.