The rapid development of the Industrial Internet of Things (IIoT) marks a major paradigm shift in the application of advanced computing technologies across industries. At the forefront of this revolution is the advanced technology of Computing in Memory (CiM), which mainly focuses on combining digital and analog approaches to improve the computational efficiency of neuromorphic processors. The goal of this study is to explore the connection between memristor-based CiM techniques and large-scale language models (LLMs) in IIoT systems, with a particular focus on memristor state-transition models and their impact on developing energy-efficient, high-performance neuromorphic processors. Experimental results show that the mobility of the memristor and the frequency of the applied voltage are important parameters of state transitions. We focus on exploring memristor’s instant saturation properties and state transition dynamics, and we investigate their potential applications in CiM-based LLMs. We analyze both multistate and dual-state memristors for analog and digital CiM, focusing on their advantages in terms of computational accuracy and power consumption for intelligent IIoT.

This article proposes a novel error correction code (ECC) module designed for future object recognition systems that are expected to utilize spin-transfer torque MRAM (STT-MRAM) for weight data storage. The module focuses on achieving high throughput and a small area while ensuring the integrity of the data. A pipelined high-parallel Bose–Chaudhuri–Hocquenghem (BCH) module is proposed to address the high throughput requirement of the ECC module in STT-MRAM. A 64-parallel linear feedback shift register for the encoder and parallel factor reduced decoder are proposed to optimize the small area requirement, however, maintain the read delay within the nanosecond level. Code length and correction capability of BCH codes are optimized, which are feasible to object recognition systems with high efficiency of memory redundancy and computational complexity. The ECC's correction performance is verified using error maps obtained from practical measurements of real-working STT-MRAM chips fabricated using 37 nm MTJ/40 nm CMOS technologies. The implementation results demonstrate that the proposed ECC module achieved the highest throughput of 64${bit} \cdot {{f}}_{{clk}}$and a small area of 18.27K$\mu {\mathrm{m}}^2$with a read latency of 5.76 ns. Practical experiments utilized error maps of STT-MRAM and MobileNet weight dataset based on CNN to verify the proposed ECC. Experiment results demonstrated the proposed ECC module achieved no accuracy degradation when the bit error rate of STT-MRAM is under 2×10-3for neural networks.

Abstract Deep neural networks (DNNs) have delivered unprecedented achievements in the modern Internet of Everything society, encompassing autonomous driving, expert diagnosis, unmanned supermarkets, etc. It continues to be challenging for researchers and engineers to develop a high-performance neuromorphic processor for deployment in edge devices or embedded hardware. DNNs’ superpower derives from their enormous and complex network architecture, which is computation-intensive, time-consuming, and energy-heavy. Due to the limited perceptual capacity of humans, accurate processing results from DNNs require a substantial amount of computing time, making them redundant in some applications. Utilizing adaptive quantization technology to compress the DNN model with sufficient accuracy is crucial for facilitating the deployment of neuromorphic processors in emerging edge applications. This study proposes a method to boost the development of neuromorphic processors by conducting fixed-point multiplication in a hybrid Q-format using an adaptive quantization technique on the convolution of tiny YOLO3. In particular, this work integrates the sign-bit check and bit roundoff techniques into the arithmetic of fixed-point multiplications to address overflow and roundoff issues within the convolution’s adding and multiplying operations. In addition, a hybrid Q-format multiplication module is developed to assess the proposed method from a hardware perspective. The experimental results prove that the hybrid multiplication with adaptive quantization on the tiny YOLO3’s weights and feature maps possesses a lower error rate than alternative fixed-point representation formats while sustaining the same object detection accuracy. Moreover, the fixed-point numbers represented by Q(6.9) have a suboptimal error rate, which can be utilized as an alternative representation form for the tiny YOLO3 algorithm-based neuromorphic processor design. In addition, the 8-bit hybrid Q-format multiplication module exhibits low power consumption and low latency in contrast to benchmark multipliers.

Next-generation industrial edge artificial intelligence (AI) applications will undoubtedly emerge on energy-efficient, highly-integrated platforms incorporating various sensors, processors, and functional modules. Embedding the data quantization module onto edge AI chips, connecting sensors, processors, and functional modules is critical to achieving adaptive transformation of diverse data representation formats. This paper proposes a novel adaptive and low-power quantization technique and systematically validates its effectiveness from algorithm to hardware module for industrial IoT applications, covering precise navigation for autonomous vehicles and accurate classification utilizing deep neural networks (DNNs). The proposed quantization method merges an adaptive conversion function from floating-point to fixed-point binaries and an adaptive radix-point determination function, ensuring adequate resolution and minimal error loss of the fixed-point inputs to the edge AI modules. The experimental results demonstrate that the quantization error in the proposed quantization technique contributes negligible errors to the navigation solutions of the strapdown inertial navigation system and the DNNs' top-1 and top-5 classification accuracy (on the order of 10$^{-8}$and 10$^{-7}$). Moreover, a quantization-on-multiplier (QoM) hardware module is designed, synthesized, and routed in accordance with the proposed quantization technique. The simulation results indicate that the QoM's power consumption and area are 0.1 mW and 649.552$\mu \text{m}^{2}$, accounting for 5% and 14.15% of its total energy consumption and area, respectively. With our proposed on-chip quantization technique, the time required to quantize the parameters of DNNs is up to 1142 times shorter than with the existing benchmark off-chip quantization approaches.

A hybrid signed convolution module with the architecture of an unsigned divide-and-conquer (UDC) multiplier is proposed to improve the functional diversity and energy efficiency of artificial intelligence (AI) accelerators based on spin-transfer-torque magnetic random access memory (STT-MRAM). The proposed UDC multiplier framework enables three multiplication modes ($n \times n$,$n \times n$/2, and$n/2\times n$/2 bit), considerably enhancing the multiplier’s versatility for next-generation AI accelerators. Compared to the state-of-the-art convolution accelerators, the UDC multiplier-based convolution module offers the lowest average power consumption for$8\times8$bit convolution. By deploying power-gating technology on STT-MRAM, the proposed convolution module preserves sufficient accuracy in high-bit multiplication while decreasing energy consumption by a factor of 22. Furthermore, incorporating a hybrid convolution module improves power efficiency by an additional$8\times $, culminating in a$175\times $decrease in power efficiency for an STT-MRAM-based AI accelerator.

In the above article[1], the reference numbers [10], [11], [12], and [13] inTable IIwere not correct and should be changed to [11], [12], [13], and [14]. The correctTable IIis illustrated as follows.

Offloading the unprecedented growing data to the edge exhibits a mainstream trend in the Industrial Internet of Things (IIoT) era, delivering far-reaching impacts in all aspects of our daily lives, including transportation, health care, and entertainment. However, voluminous data analyzes and processing at the edge will unavoidably raise the edge processor's burden and dramatically expand its design complexity and energy dissipation. This article proposes a flexible bit-adjustment-based energy-efficient convolution module with an approximate divide-and-conquer (ADC) multiplier for compact and low-power edge processor design. The maximum distribution search technique is utilized to exploit the optimal fixed-point representation format for both input and output of the convolution module. The neural network manifests the same precision as a 32-b floating-point multiplication deploying the determined representation formats. An ADC multiplier is proposed to realize the convolution module by eliminating the high-bit multiplication between weights and feature maps. The dynamic power consumption of the ADC multiplier-based convolution module with the$Q(6, 9)$input and$Q(7, 8)$output representation formats is 3.85% lower than that of the 16-b signed multiplication circuit. Furthermore, the dynamic power consumption with$Q(6, 9)$input is capable of being decreased by 15.38% for the 16-b convolution if the output is represented by the$Q(1, 14)$format and by up to 39.93% for the 64-b multiplication. The practical verification system of the convolution module working on a field-programmable gate array evaluation board exhibits an outstanding low-power characteristic.

A new VLSI CAD environment considering stochastic behavior of MTJ devices is proposed for the evaluation of not only the performance but also the reliability of MTJ/MOS-hybrid logic LSI. The proposed simulator allows users to support the design of MTJ/MOS-hybrid LSI by RTL/gate-level hardware description, whose simulation considering stochastic switching behavior of MTJ device can be done by analog-mixed-signal simulation with de-facto standard EDA tools. Through the design of a nonvolatile logic LSI based on a general purpose 32-bit microprocessor, the impact of the proposed design flow is demonstrated.

Nonvolatile spintronic devices have potential advantages, such as fast read/write and high endurance together with back-end-of-the-line compatibility, which offers the possibility of constructing not only stand-alone RAMs and embedded RAMs that can be used in conventional VLSI circuits and systems but also standby-power-free high-performance nonvolatile CMOS logic employing logic-in-memory architecture. The advantages of employing spintronic devices, especially magnetic tunnel junction (MTJ) devices with CMOS circuits, are discussed, and the current status of the MTJ-based VLSI computing paradigm is presented along with its prospects and remaining challenges.

New computer memory hierarchy based on spintronics is proposed for low-power electronics that will evolve in two steps from the current volatile system. At first, memories for internal states and pipeline registers and cache memories etc. are made nonvolatile by using spintronics. Then, computers can be made totally nonvolatile by additionally adopting spintronics-based logic-in-memory architecture. Nonvolatile MPU, recognition processor and cache memory that use magnetic tunnel junction (MTJ) have been designed and fabricated to demonstrate their superior features in low static power and high speed data store and restore operations.

A delay circuit using four-terminal magnetic-random-access-memory (MRAM) devices was designed for power-efficient time-domain signal processing. A cell area of 6.4 μm2was obtained using 90-nm CMOS/MRAM technologies. The basic operations to both store the data and control the delay time were confirmed on the fabricated test chips. In addition, we proposed a power-efficient neuromorphic core using the delay circuit.

A nonvolatile associative memory architecture based on the Magnetic Tunnel Junction (MTJ) devices has been proposed for high-speed low-power recognition. In order to reduce the power dissipation without sacrificing the speed performance, an intelligent power-saving scheme has been developed taking the advantage of non-volatility of MTJ devices. The power lines of 4-Transistor 2-MTJ nonvolatile memory cells are controlled by not only word line signals but also the internal power control signals supplied from the data-mask/power-gating units to only activate the currently accessed memory elements. The proof-of-concept chip for 128-dimension data vectors has been designed under a 90-nm 5-metal CMOS/MTJ hybrid technology, and the chip operation at 100MHz has been verified by SPICE simulation. Compared to the conventional 6T-SRAM architecture, the proposed architecture achieves the higher speed and up to 97% power reduction. Moreover, this architecture is also proved to be particularly suitable for the applications with higher dimension data vectors.

A perpendicular magnetic-tunnel-junction (MTJ)-based 2T-2R ternary content-addressable memory (TCAM) cell is proposed for a high-density nonvolatile word-parallel/bit-serial TCAM. The use of MOS/MTJ-hybrid logic makes it possible to implement a compact nonvolatile TCAM cell with 2.5 μm2of a cell size in a 0.14-μm CMOS and a 100-nm perpendicular-MTJ technologies. By reversed-current reading through the perpendicular MTJ device, tolerability of read disturb is greatly enhanced. Moreover, fine-grained power gating based on bit-level equality-search scheme achieves ultra-low activity rate of 4.1% in a fabricated 72-bit × 128-word nonvolatile TCAM, which results in ultra-low active power and standby power.

An extremely practical simulation program with integrated circuits emphasis (SPICE) incorporating model parameters of magnetic tunnel junction (MTJ) was developed. The simulator provides reliable simulation results in spintronics circuit design because it can accurately calculate various MTJ characteristics that actual devices have, that considerably influence the operation margin and power dissipation. It can also accelerate the simulation speed, which makes it possible to simulate three times or more large-scale circuits than when a conventional macro-model is used.

The compact and low power logic circuit design for multi-pillar vertical MOSFETs has been proposed. The proposed design with the multi-pillar vertical MOSFETs is very practical for considering the load capacitance and resistance by changing the number of the silicon pillars flexibly for the desired channel width of series connected MOSFETs and their layout pattern.

Nonvolatile logic-in-memory architecture, where nonvolatile memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced interconnection delay. This paper presents novel nonvolatile logic circuits based on logic-in-memory architecture using magnetic tunnel junctions (MTJs) in combination with MOS transistors. Since the MTJ with a spin-injection write capability is only one device that has all the following superior features as large resistance ratio, virtually unlimited endurance, fast read/write accessibility, scalability, complementary MOS (CMOS)-process compatibility, and nonvolatility, it is very suited to implement the MOS/MTJ-hybrid logic circuit with logic-in-memory architecture. A concrete nonvolatile logic-in-memory circuit is designed and fabricated using a 0.18 mum CMOS/MTJ process, and its future prospects and issues are discussed.

A proposed linear regulator uses a Flexible Control technique of Output Current (FCOC) to achieve 96.5% efficiency. The FCOC technique realizes to drive a flexible output current according to the output current variation and stable output voltage supply. The linear regulator fabricated by 1.2um CMOS process occupies 0.423mm 2. The fabricated linear regulator achieves 96.5% current efficiency and less than 6.81mVpp output voltage fluctuation at an output current frequency from 1.8Hz to 100 MHz.

Reliability issues for flash electrically erasable programmable read-only memories are reviewed. The reliability of both the source-erase type (ETOX) flash memory and the NAND structure EEPROM are discussed. Disturbs during programming, write/erase endurance, charge loss of both devices are reviewed, and the reliability of the tunnel oxide and the interpoly dielectric are described. It is shown that bipolarity F-N programming/erase, which is used in the NAND EEPROM, improves the charge to breakdown and decreases the stress-induced leakage current.>