Universal, semi-empirical MOSFET hole inversion layer mobility degradation models for use in circuit simulation programs such as SPICE are presented. By accurately predicting the mobility degradation due to acoustic phonon scattering and surface roughness scattering for p-channel MOSFETs at room temperature, these models eliminate the need for fitting parameters for each technology, which is required in the current SPICE level 3 model. The expressions reported accurately predict the mobility over a very wide range of channel doping concentrations, gate oxide thicknesses, gate voltage, and substrate bias, and they agree very well with recently published experimental mobility degradation data. When implemented in a circuit simulation code, these models will accurately determine the channel mobility in surface p-channel MOSFETs using only the channel doping concentration, gate oxide thickness, substate bias, and applied gate drive voltage as input parameters.>

Based on the physical insights provided by the universal mobility curve, an improved comprehensive universal model for effective electron mobility in inversion layers of n-channel MOSFETs is developed for circuit simulation. This model expresses the effective electron mobility at room temperature as a function of effective vertical field. It exhibits a high degree of accuracy for a wide range of different device characteristics, such as channel doping levels, gate oxide thicknesses, and channel dimensions. In addition, it predicts very well the effective mobility under the effects of substrate biases for gate voltages well above threshold, which is an improvement over earlier models. Moreover, this model has been developed with an emphasis on the functional dependence of mobility on high effective field, and is thus particularly accurate in that range of effective field. This is a significant advantage of the model since today's submicrometer MOSFETs typically operate at high effective fields.>

From the physical insights provided by the universal effective mobility versus effective vertical electric field curve for electrons in MOS inversion layers, a simple general expression for the gate voltage dependence of the effective electron mobility is derived for use in SPICE circuit simulation. This expression is quite accurate over a wide range of channel doping concentrations and gate oxide thicknesses, without the need for fitting parameters, such as the theta parameter of the current SPICE level 3 mobility degradation model. It is, therefore, a much more universal model than the present SPICE level 3 mobility expression. Furthermore, the relative accuracy of this new model compared to the current SPICE model is expected to increase at the higher vertical electric fields typical of submicrometer oxide semiconductor field effect transistors (MOSFETs).>

The memory cell and technology requirements and issues for 64- and 256-Mb MOS DRAMs (dynamic random-access memories) based on the charge storage concept (one-transistor cell) are analyzed. Projected requirements have been developed for key parameters such as die size, cell area, charge capacity, storage capacitance and area, leakage current, and on-current. These requirements are based on an analysis and assessment of expected improvements in soft error rate, sense amplifier sensitivity, 0-1 storage voltage difference, and bit line capacitance. Pivotal issues specific to the DRAM are identified. It is concluded that sufficient progress will be made so that 64-Mb DRAMs will be successfully produced in the early to mid-1990s.>