Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page
Demo Data from VLDB 2026 / reviewers in the wild / expert

A. Ike

dblp:28/716 · DBLP profile ↗
← Back
1ranked-venue papers
0as first author
0since 2021 · last 1995
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
speculative execution		 0.011995
Implementation Trade-Offs in Using a Restricted Data Flow Architecture in a High Performance RISC Microprocessor · ISCA 1995
Processor architecture and microarchitecture
superscalar processor		 0.011995
Implementation Trade-Offs in Using a Restricted Data Flow Architecture in a High Performance RISC Microprocessor · ISCA 1995
Processor architecture and microarchitecture › instruction set architecture › RISC
RISC processor		 0.011995
Implementation Trade-Offs in Using a Restricted Data Flow Architecture in a High Performance RISC Microprocessor · ISCA 1995

Methods — techniques the papers use, named apart from their topics

performance-cost trade-off analysis · 0.0
YearPublicationVenuePosition
1995 Implementation Trade-Offs in Using a Restricted Data Flow Architecture in a High Performance RISC Microprocessor
abstract
The implementation of a superscalar, speculative execution SPARC-V9 microprocessor incorporating Restricted Data Flow principles required many design trade-offs. Consideration was given to both performance and cost. Performance is largely a function of cycle time and instructions executed per cycle while cost is primarily a function of die area. Here we describe our Restricted Data Flow implementation and the means with which we arrived at its configuration. Future semiconductor technology advances will allow these trade-offs to be relaxed and higher performance Restricted Data Flow machines to be built.
Mike Simone, A. Essen, A. Ike, A. Krishnamoorthy, Tak Maruyama, Niteen Patkar, M. Ramaswami, Michael Shebanow, V. Thirumalaiswamy, DeForest Tovey
 ISCA3