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Ryan Barnes

dblp:280/3276 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2006
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 67% Integrated circuit design · 33%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
analog and mixed-signal circuits		 0.112006
Compact modeling of on-chip ESD protection devices using Verilog-A · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006
Electronic design automation
hardware verification and test		 0.112006
Compact modeling of on-chip ESD protection devices using Verilog-A · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006
Electronic design automation › circuit simulation › device and circuit simulation
transistor-level simulation		 0.112006
Compact modeling of on-chip ESD protection devices using Verilog-A · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2006

Methods — techniques the papers use, named apart from their topics

verilog-a behavioral modeling · 0.1response surface method · 0.1
YearPublicationVenuePosition
2006 Compact modeling of on-chip ESD protection devices using Verilog-A
abstract
A practical approach for the compact modeling of electrostatic discharge (ESD) protection devices, using the behavioral language Verilog-A, is presented. Models of the NMOS transistor, the vertical n-p-n transistor, the diode, and the resistor have been developed, suitable for circuit-level simulation. Large-signal and small-signal models are provided for transient and alternating current (ac) simulation, respectively. A self-heating model is included for accurate simulation of the device ON-resistance under transient high-current conditions.
Sopan Joshi, Ryan Barnes, Elyse Rosenbaum
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3