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Aayan Kumar

dblp:280/5404 · DBLP profile ↗
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3ranked-venue papers
1as first author
2since 2021 · last 2023
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 2 · 1 first-author · 1 since 2021Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Artificial intelligence
1 paper
Efficient and distributed learning · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 50% Embedded and real-time systems · 50%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 4 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Machine learning › Efficient and distributed learning › model compression › quantization › low-precision computation
fixed-point quantization
0.412020
Shiftry: RNN inference in 2KB of RAM · Proc. ACM Program. Lang. 2020
Machine learning › Efficient and distributed learning
model compression
0.412020
Shiftry: RNN inference in 2KB of RAM · Proc. ACM Program. Lang. 2020
Hardware accelerators and domain-specific architectures › machine learning accelerator › DNN inference
edge inference
0.412020
Shiftry: RNN inference in 2KB of RAM · Proc. ACM Program. Lang. 2020
Embedded and real-time systems › embedded software engineering › embedded software development
microcontroller deployment
0.412020
Shiftry: RNN inference in 2KB of RAM · Proc. ACM Program. Lang. 2020

Methods — techniques the papers use, named apart from their topics

float-to-fixed conversion · 1.3RAM management · 1.3
YearPublicationVenuePosition
2023 MinUn: Accurate ML Inference on Microcontrollers
abstract
Running machine learning inference on tiny devices, known as TinyML, is an emerging research area. This task requires generating inference code that uses memory frugally, a task that standard ML frameworks are ill-suited for. A deployment framework for TinyML must a) be parametric in the number representation to take advantage of the emerging representations like posits, b) carefully assign high-precision to a few tensors so that most tensors can be kept in low-precision while still maintaining model accuracy, and c) avoid memory fragmentation. We describe MinUn, the first TinyML framework that holistically addresses these issues to generate efficient code for ARM microcontrollers (e.g., Arduino Uno, Due and STM32H747) that outperforms the prior TinyML frameworks.
Shikhar Jaiswal, Rahul Kranti Kiran Goli, Aayan Kumar, Vivek Seshadri, Rahul Sharma 0001
LCTES3
2021 MAFIA: Machine Learning Acceleration on FPGAs for IoT Applications
abstract
Recent breakthroughs in ML have produced new classes of models that allow ML inference to run directly on milliwatt-powered IoT devices. On one hand, existing ML-to-FPGA compilers are designed for deep neural-networks on large FPGAs. On the other hand, general-purpose HLS tools fail to exploit properties specific to ML inference, thereby resulting in suboptimal performance. We propose MAFIA, a tool to compile ML inference on small form-factor FPGAs for IoT applications. MAFIA provides native support for linear algebra operations and can express a variety of ML algorithms, including state-of-the-art models. We show that MAFIA-generated programs outperform best-performing variant of a commercial HLS compiler by 2.5 × on average.
Nikhil Ghanathe, Vivek Seshadri, Rahul Sharma 0001, Steve Wilton, Aayan Kumar
FPL5
2020 Shiftry: RNN inference in 2KB of RAM
abstract
Traditionally, IoT devices send collected sensor data to an intelligent cloud where machine learning (ML) inference happens. However, this course is rapidly changing and there is a recent trend to run ML on the edge IoT devices themselves. An intelligent edge is attractive because it saves network round trip (efficiency) and keeps user data at the source (privacy). However, the IoT devices are much more resource constrained than the cloud, which makes running ML on them challenging. Specifically, consider Arduino Uno, a commonly used board, that has 2KB of RAM and 32KB of read-only Flash memory. Although recent breakthroughs in ML have created novel recurrent neural network (RNN) models that provide good accuracy with KB-sized models, deploying them on tiny devices with such hard memory requirements has remained elusive. We provide, Shiftry, an automatic compiler from high-level floating-point ML models to fixed-point C-programs with 8-bit and 16-bit integers, which have significantly lower memory requirements. For this conversion, Shiftry uses a data-driven float-to-fixed procedure and a RAM management mechanism. These techniques enable us to provide first empirical evaluation of RNNs running on tiny edge devices. On simpler ML models that prior work could handle, Shiftry-generated code has lower latency and higher accuracy.
Aayan Kumar, Vivek Seshadri, Rahul Sharma 0001
Proc. ACM Program. Lang.1