Fault-tolerant technology is becoming increasingly critical due to the growing complexity of computing systems and escalating demands for reliability. Conventional recovery mechanisms in asymmetric multiprocessor systems often incur substantial overhead or exhibit inefficiencies, such as prolonged rollback latency and complex synchronization protocols. This paper introduces an adaptive fast recovery scheme based on checkpoints that minimizes reliance on rollback by prioritizing roll-forward execution where feasible, while retaining rollback capabilities for severe failures. Using a triple modular redundancy system as a case study, we comprehensively detail the proposed scheme’s operation. By modeling fault occurrences via a Poisson process, we theoretically analyze the performance of conventional rollback algorithms against the proposed strategy. The scheme is implemented on an FPGA platform with heterogeneous processors (ARM, MIPS, and RISC-V), demonstrating practical synchronization across diverse architectures. Experimental results demonstrate that our scheme achieves over 10% reduction in average execution time compared to traditional rollback methods, thereby providing an efficient and hardware-validated fault-tolerant solution for advanced multiprocessor systems.

To deploy SRAM-based FPGAs as platforms for aerospace applications, the reliability of designs should be ensured, since FPGAs are susceptible to radiation-induced single-event upsets (SEUs). SEUs can cause configuration corruption and further functional failure. Triple modular redundancy (TMR) is often used to mitigate this risk. However, common mode failure, which is an inherent flaw of the traditional TMR architecture, limits the effectiveness of mitigating SEUs. Therefore, aiming at CPU-centric TMR systems, we propose an approach to restructure the redundant modules in the TMR architecture. Three instruction set architecture (ISA)-heterogeneous CPUs, which are functionally equivalent, introduce difference into the utilization of configuration memory, and thus eliminate the common mode failure. Further, we propose an analytical method based on Markov model to estimate the SEU reliability for both TMR architectures, and efficiently prove the SEU reliability improvement of the ISA-heterogeneous TMR architecture. Finally, by investigating the derived SEU reliability, we offer guidance on how to design an ISA-heterogeneous TMR system to realize higher reliability.