In this brief, the thermal performance of a large-scale cloud server system-on-chip (SoC) with the backside power delivery network (BS-PDN) and 3-D integration in memory-on-logic (MoL)/logic-on-memory (LoM) configuration with 2.5-D packaging is analyzed in advanced A10 nanosheet technology node using Sentaurus TCAD platform. The results show a 45.6% (~20.3 K) thermal penalty for the 80-core SoC in MoL with BS-PDN compared with the 2-D-baseline frontside PDN (FS-PDN), using a heatsink with forced cooling. A nonuniform power map further aggravates thermal concerns, which can be mitigated using an LoM configuration with BS-PDN, reducing the penalty to 22% (~15 K). Extending the study to a 320-core SoC, in conjunction with an advanced cooling system, LoM with BS-PDN shows 45.3% (~29 K) lower temperature than conventional MoL BS-PDN. The modeling results provide valuable insights and motivate future research into packaging and cooling techniques for BS-PDN integration.

Digital Low Dropout Regulators (LDOs) are an excellent candidate for area-efficient fine-grain power management in heterogeneous systems, leveraging integrated power switches. Relocating the power switches to the backside of the wafer in conjunction with the Backside Power Delivery Network (BSPDN) layer is envisaged as a System Technology Co-Optimization (STCO) booster for finer grain power management and reduced area/cost. We perform a detailed thermal analysis using power-switch-based LDOs enabling per-core DVFS for a high-performance server 3D computing chiplet in a Nanosheet CMOS (A10) technology node with BSPDN. While BSPDN introduces thermal penalties due to a lack of lateral heat spreading, our high-resolution thermal simulations explore the feasibility of moving LDOs to the backside. Increasing the LDO area from 5% to 50% of the backside die area effectively lowers the 2.5/3D System-in-Package (SiP) peak temperature, confirming that thermal concerns do not impede backside LDO integration. This study supports the cost-effective design of next-generation SiPs by demonstrating no adverse thermal impact for relocating power switches to the wafer backside in the nanosheet era.

Static RAM (SRAM) is one of the critical components in advanced VLSI systems whose performance, capacity, and reliability have a decisive impact on the entire system. It offers the fastest memory in the storage hierarchy of modern computer systems. By moving toward the smaller CMOS technology nodes, the back end of the line (BEoL) interconnects are also fabricated in tighter pitch size. Hence, besides the power lines, SRAM word- and bit-line (WL and BL) are also susceptible to electromigration (EM). Therefore, EM reliability of SRAM's WL and BL needs to be analyzed during design technology co-optimization (DTCO) cycle. In this work, we investigate the impact of technology scaling on SRAM designs and perform a detailed analysis on the trend of their EM reliability and energy consumption. Our analysis shows that although scaling down the CMOS technology can result in a 2.68x improvement in the energy efficiency of the SRAM module, it increases the EM-induced hydrostatic stress by 2.53x.

Due to technology scaling in modern computing platforms, the safety and reliability issues have increased tremendously, which often accelerate aging, lead to permanent faults, and cause unreliable execution of applications. Failure in some computing systems like avionics may cause catastrophic consequences. Therefore, managing reliability under all circumstances of stress and environmental changes is crucial in all abstraction layers, from application to transistor levels. Machine learning techniques are recently being employed for dynamic reliability estimation and optimization. They can adapt to varying workloads and system conditions. This paper presents reliability improvement approaches from multiple perspectives-from transistor-level to application-level-and discusses their effectiveness and limitations as well as open challenges.

Due to the rise in the number of cores in modern multicore architectures, 3-D integration (i.e., vertical stacking of chips) of system-on-a-chip (SOC) promises better performance due to a drastic reduction in global interconnect lengths and die footprint compared with 2-D counterparts. However, thermal issues are predominant in 3-D-SOCs due to the vertical stacking nature of chips which multiplies the transistor power density by the number of dies within the stack. Also, the reduced lateral heat spreading with aggressive die thinning degrades the ON-chip thermal performances. In this article, we investigate the thermal performance analysis of 3-D-SOC and compare the results with the 2-D-SOC designs for a MemPool multicore SOC with shared L1 scratchpad memory (SPM). Simulation results reveal that the 3-D-SOC using memory-on-logic (MOL) configuration increases the ON-chip maximum temperature by more than 20% compared with the baseline 2-D-SOC and the logic die temperature is relatively higher (3.6%) than the memory die. We also explore the impact of architectural floor-planning effects and 3-D functional partitioning on thermal performance of the MemPool instances in the 3-D-SOC with memory capacity ranging from 1 to 8 MiB and benchmarked the thermal performance with the 2-D-SOC designs. We observe that the junction-to-ambient temperature ($T_{\max }$) increases by 44% and is predominant for the SPM capacity of 8 MiB. Further investigations on various 3-D stacking configurations reveal there is an improvement in thermal performance for MOL over logic-on-memory (LOM) for L1 SPM capacity of 1, 2, and 4 MiB, and LOM over the MOL configuration for L1 SPM capacity of 8 MiB.

Energy saving is important for both high-end processors and battery-powered devices. However, for time-critical application such as car auto-driving systems and multimedia streaming, saving energy by slowing down speed poses a threat to timing guarantee of the applications. The worst-case execution time (WCET) is a widespread solution to this problem, but its static execution time model is not sufficient anymore for highly dynamic hardware and applications nowadays. In this work, a fully proactive run-time mitigation methodology is proposed for energy saving while ensuring timing guarantee. This methodology introduces heterogeneous datapath options, a fast fine-grained knob which enables processors to switch between datapaths of different speed and energy levels with a switching time of only tens of clock cycles. In addition, a run-time controller using a dynamic scenario methodology is developed. This methodology incorporates execution time prediction and timing guarantee criteria calculation, so it can dynamically switch knobs for energy saving while rigorously still ensuring all timing guarantees. Simulation shows that the proposed methodology can mitigate a dynamic workload without any deadline misses, and at the same time energy can be saved.

Ensuring a timing guarantee is crucial for time-critical applications. However, this task becomes more challenging with the increasing performance variability generated by complicated modern hardware and software. A widespread solution to the problem is real-time scheduling, which depends on worst-case execution time (WCET) and dynamic voltage frequency scaling (DVFS). Although these techniques provide the necessary guarantees, they also exhibit important limitations from the long switching time of DVFS and the overly pessimistic execution time model of WCET. In this work, a multitimescale mitigation methodology is proposed to improve the way of tackling performance variability in both timing guarantee and energy saving. By using both the DVFS and heterogeneous datapath (HDP) knobs, this methodology can push the timescale of mitigation down to the submillisecond level. Moreover, this methodology can calculate a tight upper bound of execution time at run-time using dynamic scenarios (DSs). Simulation shows that the proposed methodology can ensure zero deadline misses with a smaller safety time margin than the method using only DVFS and WCET. This advantage can translate into an energy reduction by half compared to the conventional WCET-based method with a single DVFS knob.

The presence of multiple cores in modern multicore architectures makes thermal management and temperature estimation a really challenging task for enhancing reliability and lifespan. Due to the presence of many cores, the core/tile spacing needs to be optimized in order to enhance the thermal coupling between interconnect routing blocks and active tiles. In addition, the tiles activity patterns under partial workload conditions significantly affect the maximum on-chip temperature which results in nonuniform temperature distribution. This is due to poor thermal coupling between neighboring tiles owing to the decrease in spacing between cores. In this article, we investigate the thermal performance analysis of a 256-core (i.e., 64 tiles) Mempool reduced instruction set computer (RISC) V-based architecture considering the impact of inter tiles spacing. Simulation results reveal that lateral heat spreading predominantly affects the thermal performance in multicore architectures under partial workload conditions. We also optimize the thermal performance with different tiles activity pattern. Simulation results reveal that both the maximum on-chip temperature and lateral heat spreading are improved for specific tiles activity patterns. Also the thermal performance analysis considering the “tile-insite effect” reveals that there is little impact on on-chip maximum temperature ($T_{\text {max}}$), but the on-chip thermal gradient ($\Delta T$) and the thermal profile pattern are predominantly affected. Finally, the effect of the secondary heat path toward printed circuit board (PCB) is studied in this work.