The IEEE European Test Symposium (ETS) has been facilitating progress in electronic systems testing since its launch in 1996. On the occasion of its 30th anniversary, this collaborative paper gathers sections by 21 ETS teams to outline their influential ideas and milestones. Each team’s section highlights historical perspective, current research, frameworks and projects as well as forward-looking research agendas in the area of electronic-based circuits and systems testing, reliability, safety, security and validation. This anniversary summary documents how research of various ETS teams, exemplifying the test community, has been evolving and transitioning from concepts to practical standards and Electronic Design Automation (EDA) tools and flows. This legacy is a strong base to drive the next generation of advances in electronic systems testing.

Modern analog mixed-signal (AMS) devices manufactured in advanced CMOS processes pose significant testing and post-manufacture tuning challenges. Measurement of the specifications of AMS components is generally difficult as this requires the use of a range of dedicated tests while defect-based testing on the other hand, requires extensive defect simulations that are compute-intensive. To overcome these limitations, this research proposes OATT; a testing and post-manufacture tuning approach for AMS circuits that is designed to stress the performance of the device under test (DUT), formalize a statistical (multidimensional Gaussian) distribution of the expected response of known “good” devices (inliers), and use test limits grounded in theoretical statistics to classify all out-of-distribution devices (outliers) as “bad.” It is an alternative test approach in that it does not explicitly target simulation of defect mechanisms. Tuning is performed to transform individual outlier DUT responses to those resembling inlier devices by modulating hardware tuning knobs, such as bias voltages and currents, using a reinforcement learning algorithm. Circuit simulations and hardware results demonstrate the viability and efficiency of the proposed approach.

Modern wireless communications systems deploy massive MIMO systems with large numbers of transmit and receive antennas and analog–digital RF transceiver architectures that admit RF beamforming. These systems need to be tested and tuned postmanufacture to ensure signal quality. In analog architectures, this poses a problem due to the lack of observability of internal circuit nodes and due to the convergence of multiple RF beamforming chains into a combined baseband signal from which it is difficult to de-embed individual RF chain behaviors. Existing test techniques estimate nonlinearities in RF chains up to the third order and require significant frequency bandwidth to test multiple RF chains in a MIMO system in parallel, thereby reducing the overall test time. In this research, to improve testing efficiency, overlapping test tones over a minimal frequency range are applied to each of the MIMO RF chains in parallel, allowing specifications of individual RF chains up to fifth-order distortion to be determined accurately. For postmanufacture tuning, a response feature clustering approach followed by an implicit cost-driven tuning procedure is proposed. Tuning for error vector magnitude (EVM) and signal-to-interference ratio (SiNR) is performed under power constraints. Experimental results show that the proposed parallel testing methodology is 1.7$\times$more frequency-efficient than existing techniques, and the proposed postmanufacture tuning algorithm can tune a receiver with four RF chains in 1.8 ms.

Prevalent test strategies for analog/mixed-signal systems rely on either (a) prediction of device-under-test (DUT) design specifications from observed test responses to carefully crafted alternate test stimulus, or (b) detecting outliers from known optimized test response statistics of devices subjected to expected manufacturing process variations. In both of these test paradigms, misclassification of DUTs (false positives and false negatives) is not explicitly considered during test generation itself due to computational complexity, but rather based on post-test determination of test acceptance thresholds. In this paper, we propose a novel test generation approach based on hyperdimensional clustering, that explicitly targets DUT misclassification rate during test stimulus generation itself. The use of hyperdimensional vectors for clustering good and bad devices along with a set of simple vector operations for training and inference allows fast determination of misclassification rate within the test generation procedure itself. Experimental results show that the test generation times are reduced by 15X with significant improvements in DUT misclassification rate.

Process variability effects and subtle defect mechanisms in deeply scaled analog/mixed-signal/RF (AMS) silicon technologies combine in malicious ways to increase DPPMs of mixed-signal Systems-on-Chips (SoCs). This has driven the need to increase defect coverage while minimizing testing costs. However, testing embedded AMS components in mixed-signal SoCs has always been a challenge due to test access limitations and requirement for labeled data. In this work, we focus on eliminating the requirement for labeled data. As such, rather than measuring the specification values of embedded AMS components, it is more expedient to devise tests using on- chip resources along with low cost mechanisms for identifying outlier behaviors in measured data to identify devices with parametric and catastrophic defects. To resolve this, what is needed are : (a) a test generation methodology that separates outlier from inlier device behaviors making them easily detectable and (b) a response analysis approach that can draw boundaries between multi-dimensional "good" and "outlier" behaviors with such computational ease that it can be invoked in each test generation iteration to quantify the quality of the test being considered. In this context, a novel test stimulus generation approach using clustering of test data in hyperdimensional spaces is developed that maximizes the similarities of inlier devices in the hyperdimensional space thereby allowing outlier devices to be identified easily by their corresponding hypervector representations from their dissimilarity with hypervectors of inlier devices. Such an approach overcomes the major drawback of prior approaches by eliminating the requirement for labeled data. For decision-making, a one-class hyperdimensional classifier that relies on a single cluster boundary (as opposed to complex boundaries in nonlinear spaces), is used to separate "good" vs. "bad" devices. The classifier is computationally efficient, outperforms existing techniques for defect coverage, and drives the search for the optimal test stimulus. Simulation results on test circuits prove the benefits of the proposed approach over prior testing methods.

Prevalent specification-based AMS testing techniques require the use of complex test circuits or regressors that are difficult to implement on-chip as well as suffer from coverage loss when devices are under-specified. Complementary defect based testing techniques require the simulation of explosively large defect sets under assumed failure mechanisms. We overcome these limitations in our proposed approach OATT; an Outlier-oriented Alternative Testing and Tuning methodology. OATT maximizes the number and magnitude of the statistical principal components (PCA) of the time-domain DUT test response vectors across diverse manufacturing process corners. This allows construction of a multi-dimensional Gaussian probability density model that characterizes the distribution of DUT responses in the principal components domain. Outliers of this probability density model are classified as defective devices using calibrated confidence ellipses, implicitly detecting devices with parametric as well as hard defects. The embedded DUT response is acquired using coherent undersampling and does not require explicit signal reconstruction. Post-manufacture tuning is performed by minimizing the statistical distance of the DUT response in the PCA domain from the nominal Gaussian model using multi-arm bandit reinforcement learning. Simulation results demonstrate the viability and promise of the proposed approach.

Emerging wireless technologies employ MIMO beamforming antenna arrays to improve channel Signal-to-Noise Ratio (SNR). The increased dynamic range of channel SNR values that can be accommodated, creates power stress on Radio Frequency (RF) electronic circuitry. To alleviate this, we propose an approach in which the circuitry along with other transmission coding parameters can be dynamically tuned in response to channel SNR and beam-steering angle to either minimize power consumption or maximize throughput in the presence of manufacturing process variations while meeting a specified Bit Error Rate (BER) limit. The adaptation control policy is learned online and is facilitated by information obtained from testing of the RF circuitry before deployment.

Modern 5G and projected 6G wireless systems deploy massive MIMO systems with antenna arrays and novel RF transceiver architectures that admit RF beamforming. Testing and tuning of the underlying transceiver arrays on a per-transceiver basis is expensive and can be expedited through the use of parallel testing and tuning techniques that stimulate the entire array transceiver system concurrently. State of the art parallel testing techniques require frequency separation between the tones applied to individual RF chains due to combining of RF signals before down-conversion in analog beamforming MIMO systems. Test schemes that allow some frequency overlap are limited to testing only third order distortion. In this paper, we first present a parallel testing scheme for testing large MIMO transceiver arrays that is amenable to higher order distortion (upto fifth order) in the RF chains considered. Second, we propose a tuning scheme for the entire MIMO array which implicitly tunes for EVM system specifications without explicit knowledge of the relationship between the system test response, the system tuning knobs and the corresponding EVM and SINR specification values. A cost metric is formulated that allows such a solution using reinforcement (multi-arm bandit) learning driven system tuning. Significant yield improvement using this approach is demonstrated by simulation experiments.