Memristor-based neural networks promise low-power, high-density neuromorphic hardware, yet most studies remain proof-of-concept with small inputs and qualitative reporting. We present a comprehensive investigation of on-chip learning in a scalable memristor network, modeling realistic non-idealities including device-to-device and cycle-to-cycle variability, conductance programming errors, and input noise. Using a 30-memristor architecture, we systematically scale inputs from 3×3 to 11x11 and evaluate classification robustness under noisy conditions. Results show that moderate training noise improves tolerance, enabling up to 99% accuracy with 20% noisy tests, whereas aggressive weight quantization at higher resolutions can degrade accuracy. We quantify average training time and energy across device types; chromium devices are most efficient, achieving 2.4 s average training time and 18.9mJ training energy for 3×3 tasks. We also report energy per classification versus input size, establishing concrete benchmarks often absent from prior work. A Big-O analysis indicates sub-linear growth of training time (n0.26), training energy (n0.28), and inference cost with input dimension, supporting suitability for edge deployment. Unlike earlier demonstrations that emphasized qualitative recognition, this study provides quantitative trade-offs among accuracy, noise robustness, energy, and training time, bridging device-level feasibility and practical memristor neural network accelerators. These results guide design choices for deployable edge systems.