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Gary W. Leive

dblp:287/0476 · DBLP profile ↗
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3ranked-venue papers
1as first author
0since 2021 · last 1983
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Electronic design automation · 90% Processor architecture and microarchitecture · 10%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › high-level synthesis › scheduling and allocation
module selection		 0.021983
Automating Technology Relative Logic Synthesis and Module Selection · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983
A technology relative Logic Synthesis and Module Selection system · DAC 1981
Electronic design automation
high-level synthesis		 0.021983
Automating Technology Relative Logic Synthesis and Module Selection · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983
The CMU design automation system: An example of automated data path design · DAC 1979
Electronic design automation
logic synthesis		 0.021983
A technology relative Logic Synthesis and Module Selection system · DAC 1981
Automating Technology Relative Logic Synthesis and Module Selection · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983
Electronic design automation › logic synthesis
technology mapping		 0.011981
A technology relative Logic Synthesis and Module Selection system · DAC 1981
Processor architecture and microarchitecture › microprocessor design › processor core design
datapath design		 0.011979
The CMU design automation system: An example of automated data path design · DAC 1979

Methods — techniques the papers use, named apart from their topics

design space prediction · 0.0constraint-driven methodology · 0.0
YearPublicationVenuePosition
1983 Automating Technology Relative Logic Synthesis and Module Selection
abstract
This paper discusses a design aid which translates the data part of a functional level digital design into a logic level design through the specification of module set information. The constraint driven automatic methodology is discussed and results of using the design aid are presented. Predictors are developed to estimate the logic level design space, thus providing early feedback within the design process.
Donald E. Thomas, Gary W. Leive
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
1981 A technology relative Logic Synthesis and Module Selection system
Gary W. Leive, Donald E. Thomas
 DAC1
1979 The CMU design automation system: An example of automated data path design
Alice C. Parker, Donald E. Thomas, Daniel P. Siewiorek, Mario Barbacci, Louis J. Hafer, Gary W. Leive, Jinchoon Kim
 DAC6