Cryptography primitives have a prominent role in securing applications that may require low-area realizations, for example portable devices and other resource constrained devices. A given system may require support for different cryptography based protocols/ primitives. Many standardized and/or published primitives rely on arithmetic operations over$GF\left ({2^{m}}\right)$that occupy major area footprint. Therefore, versatile operators have been of interest to reduce the area penalty, in particular bit-serial multipliers. This paper introduces a novel scheme for versatile multiplication by the normal element in the Gaussian Normal Basis (GNB) leading to new low-area versatile GNB multiplier and inverter architectures that are presented for the first time, as far as we know. Specifically, the proposed inverters are the first versatile GNB inversion in open literature, to the best of our knowledge. Field Programmable Gate Arrays (FPGA) implementation results demonstrate that the proposed versatile multiplication and inversion techniques save almost 30% and 46%, and for Application Specific Integrated Circuits (ASIC) implementation the savings are up-to 29% and 35% respectively, in terms of area when compared to other counterparts.

Security protocols such as Transport Layer Security implement the Elliptic curve digital signature algorithm (ECDSA) over different binary extension fields defined by the National Institute of Standards and Technology (NIST). Specifically, such multiple cipher-suite support is a security recommendation. Binary extension field arithmetic processors are expensive, especially if more than one field is supported. In this context, this article introduces a novel lightweight digit-serial parallel-in-serial-out (DS-PISO) design for versatile multiplication (DS-VPISO) targeting the NIST-like fields in resource constrained embedded systems where the crypto module allocation is limited. The proposed DS-VPISO multiplier offers competitive area (up to 40 percent area savings) compared to existing multiple field multiplier schemes based on results conducted on bit-serial implementations using Intel's Field programmable gate arrays. The article first presents a DS-PISO self-dual Gaussian normal basis multiplication architecture based on the trace mapping. After this, the article extends the new trace based DS-PISO multiplier to construct an architecture for the first versatile DS-PISO multiplication (DS-VPISO) targeting NIST's binary fields. The latter extension to versatile multiplication is based on novel architectures for versatile cyclic shifts and versatile multiplication by normal elements.