The exponential growth in test data volume for modern Systems-on-Chip (SoCs), combined with a decreasing number of available test pins, has led to increased test time and complexity. Simultaneously, the industry’s drive for higher quality and lower Defective Parts Per Million (DPPM) necessitates continuous monitoring, testing, and repair Silicon Lifecycle Management (SLM). The advent of multi-die packaging technologies, such as 2.5D and 3D stacked integration, further exacerbates these challenges by introducing additional layers of interconnect and access constraints.Universal Chiplet Interconnect Express (UCIe) emerges as a compelling solution for delivering test content to all constituent dies at-speed, post-packaging. UCIe enables seamless test access across various lifecycle stages, including wafer sort, package test, System Level Test (SLT), and In-System Test (IST).This paper introduces a silicon-proven methodology that integrates the UCIe protocol with advanced SLM techniques to address the critical challenges of access, test, measurement and repair in complex multi-die SoC designs. Silicon results from test vehicles fabricated on TSMC N3P process with CoWoS-S packaging demonstrate complete interconnect, logic, and memory test, repair, and monitoring capabilities, validating the effectiveness and scalability of the proposed approach for next- - generation multi-die systems.

Rapid yield ramp-up and precise defect identification are crucial in advanced semiconductor development, especially as technologies reach 5nm and below. Scan-based testing, the primary Design for Testability (DFT) method, is essential, but scan chains are susceptible to defects, hindering yield learning. Traditional fault isolation, like Laser Voltage Probing, is ineffective in more advanced processes due to backside power rail constraints. Hardware solutions impact power, performance, and area (PPA), while software lacks accuracy. This paper introduces two methods to improve scan chain diagnosis: a multi-mode scan design with soft repair capability and a hybrid hardware-software approach. The multi-mode design identifies defective scan cells, aiding logic yield learning before Physical Failure Analysis (PFA), achieving a 100% predicted PFA success rate. The hybrid scalable method uses hardware for coarse diagnosis with minimal PPA impact and software for detailed analysis, leveraging existing test patterns. These approaches enhance scan chain diagnosis, supporting faster yield ramp-up and defect identification.

System-on-Wafer (SoW) technology integrates multiple chiplets onto a single wafer substrate, offering enhanced performance for high-computation applications. This paper presents an innovative 3D test access architecture designed for complex SoW systems. The proposed omnidirectional test access architecture, compliant with IEEE Std. 1838, provides a scalable, plug-and-play testing solution for comprehensive multi-directional testing. It enables efficient scan path configuration, optimizing test scheduling while reducing power consumption and minimizing timing-related impacts. A case study involving a SoW system with four chiplets arranged in a 2x2 configuration validates the architecture's feasibility and effectiveness, demonstrating its potential to enhance SoW testability and reliability.

Scan design adversely affects design performance, including speed, power, and routing congestion. Scan partitioning and reordering are required to mitigate these effects. We present an unsupervised machine learning-based method for scan partitioning to reduce the total scan wire length and make scan chains as compact as possible. For scan partitioning, we use the K-Means clustering method and reorder flops in a scan chain using the Traveling Salesman Problem (TSP) algorithm. Experimental results for three CPU designs show that significant savings in real wire length (2-3%), as well as a reduction in timing impact (27%), can be achieved with the proposed method compared to the best case obtained by a commercial EDA flow. Additionally, the optimized scan stitching also helped improve Design Rule check (DRC) violations, which aids in design closure.

A multi-die 3DIC is constructed by integrating multiple dies into a stack. These dies are interconnected via die-to-die (D2D) interconnects facilitated by I/O pads, which manage signal load and provide electrical protection to both the die and the overall system. The number of D2D interconnects is anticipated to increase significantly, rising from a few thousand today to several hundred thousand in the coming years. Consequently, ensuring the functionality and performance of 3DIC systems requires rigorous testing of not only the die logic but also the pads and interconnects at both the die and stack levels. In this paper, we explore the Design for Test (DFT) and testing challenges involved in handling various types of pads, ranging from simple to complex custom designs, within a multi-die 3DIC system. We also examine the tools and methodologies provided by Electronic Design Automation (EDA) tools to support these challenges, specifically focusing on implementations compliant with the IEEE 1838 standard.

In multi-die systems, interconnect clusters on chiplets are arranged in bump array patterns, and testing these interconnects for defects like shorts and opens is crucial for ensuring communication among different dies. Various ATPG algorithms have been developed to cover these defects. This paper introduces a fully automated EDA tool flow that utilizes the 3Dblox Open Standard to extract the physical location of interconnects and generate physical-aware test patterns. This optimized approach ensures comprehensive testing of all critical D2D interconnects, essential for a defect-free 3DIC system.

Heterogeneous three-dimensional (3-D) package-level integration plays an increasingly important role in the design of higher functional density and lower power processors for general computing, machine learning and mobile applications. In TSMC's 3DFabricTM platform, the back end packaging technology Chip-on-Wafer-on-Substrate (CoWoS®) with the integration of High-Bandwidth Memory (HBM) has been successfully deployed in high performance compute and machine learning applications to achieve high compute throughput, while Integrated Fan-Out (InFO) packaging technology is widely used in mobile applications thanks to its small footprint. System on Integrated Chips (SoIC⃨), leveraging advanced front end Silicon process technology, offers an unprecedented bonding density for vertical stacking.

Chip designers typically do not consider design-for-diagnosis (DfD) for manufacturing defects while implementing an integrated circuit and its design-for-test features. The lack of emphasis on DfD results in low diagnosis resolution and limited physical failure analysis (PFA) success rate when diagnosis is carried out using advanced techniques. To the best of our knowledge, no practical solution is available today to analyze the diagnosability of a design and improve it before tapeout. Furthermore, techniques that are specific to a given design cannot be reused for other chips. Therefore, we first propose a general structure-based diagnosability scoring model that can be used to analyze the diagnostic resolution for any chip. After the diagnosability analysis, we consider inserting additional observation points (OPs) for diagnosability enhancement. Given a constraint on the maximum number of inserted OPs, we propose a three-stage OP insertion (OPI) method, which includes: (i) selection of hard-to-diagnose (HTD) faults; (ii) mixed location ranking based on a structure-based diagnosability “repair” scoring model; (iii) information update and final location selection for a better diagnosability “repair” effect. The use of OPI results in higher fault “repair” rates and significant improvement in diagnosability. Experiments on benchmark circuits and industrial designs demonstrate the effectiveness of the proposed DfD solution.

3DIC technology presents a new system integration strategy for the electronics industry to achieve superior system performance with lower power consumption, higher bandwidth, smaller system form factor, and shorter time to market through heterogeneous integration. TSMC's “Chip-on-Wafer-on-Substrate (CoWoS)” technology opens up a new opportunity to bring 3D chip stacking vision from concept to reality. The provided methodology will be discussed about this market trend and the different pieces needed to jointly make it a success, which includes customers' required application, TSMC's support design flow, as well as the ecosystem design enablement of multi-die implementation, DFT solution, thermal analysis, verification and new categories of IPs.

Recent advances in semiconductor process technology especially interconnects using Through Silicon Vias (TSVs) enable the heterogeneous system integration where dies are implemented in dedicated, optimized process technologies and stacked in a 3D form. TSMC has developed the CoWoS™ (Chip on Wafer on Substrate) process as a design paradigm to assemble silicon interposer-based 3D ICs. To reach quality requirements for volume production, several test challenges related to 3D ICs need to be addressed. This paper describes the test and debug strategy used in designing a CoWoS™ based stacked IC. The 3D design presented in the paper contains three heterogeneous dies (a logic, a DRAM, and a JEDEC Wide-I/O compliant DRAM) stacked on the top of a passive interposer. For passive interposer testing, a novel test methodology called Pretty-Good-Die (PGD) test is presented, while for inter-die test, a novel scalable multi-tower 3D DFT architecture is presented. Silicon results show that most of the test challenges can be solved efficiently if planned properly; and 3D ICs are reality and not a fiction anymore.

Three-dimensional (3D) die stacking is an emerging integration technology which brings benefits with respect to heterogeneous integration, inter-die interconnect density, performance, and energy efficiency, and component size and yield. In the past, we have described, for logic-on-logic die stacks, a 3D DfT (Design-for-Test) architecture and corresponding automation, based on die-level wrappers. Memory-on-logic stacks are among the first 3D products that will come to the market. Recently, JEDEC has released a standard for stackable Wide-I/O Mobile DRAMs (Dynamic Random Access Memories) which specifies the logic-memory interface. The standard includes boundary scan features in the DRAM memories. In this paper, we leverage and extend the 3D DfT wrapper for logic dies, such that, in conjunction with the boundary scan features in the Wide-I/O DRAM(s) stacked on top of it, testing the logic-memory interconnects is enabled. A dedicated Interconnect ATPG (Automatic Test Pattern Generation) algorithm is used to deliver effective and efficient dedicated test patterns. We have verified our proposed DfT extension on an industrial design and shown that the silicon area cost of the extended wrapper with JEDEC Wide-I/O interconnect test support is negligible.