Demo Data from VLDB 2026 / reviewers in the wild / expert
Wing H. Huen
dblp:29/102
· DBLP profile ↗
3ranked-venue papers
1as first author
0since 2021 · last 1982
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-authorComputer networks · 1Software engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Parallel and multicore computing · 42% Embedded and real-time systems · 31% Integrated circuit design · 10% | |
| Theoretical computer science
1 paper |
Algorithms and data structures · 100% |
Topics — the 7 heaviest of 9, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Embedded and real-time systems › real-time control
real-time distributed control |
0.0 | 1 | 1982 | Software Structure of No. 5 ESS-A Distributed Telephone Switching System · IEEE Trans. Commun. 1982 |
Parallel and multicore computing
software partitioning |
0.0 | 1 | 1982 | Software Structure of No. 5 ESS-A Distributed Telephone Switching System · IEEE Trans. Commun. 1982 |
Algorithms and data structures › combinatorial algorithms
enumeration algorithms |
0.0 | 1 | 1980 | Distributed Enumaration on Between Computers · IEEE Trans. Computers 1980 |
Distributed systems › concurrency control
deadlock detection |
0.0 | 1 | 1974 | Intermodule Protocol For Register Transfer Level Modules: Representation and Analytic Tools · ISCA 1974 |
Electronic design automation › hardware verification and test
hardware verification |
0.0 | 1 | 1974 | Intermodule Protocol For Register Transfer Level Modules: Representation and Analytic Tools · ISCA 1974 |
Integrated circuit design › digital system design
register-transfer level design |
0.0 | 1 | 1974 | Intermodule Protocol For Register Transfer Level Modules: Representation and Analytic Tools · ISCA 1974 |
Embedded and real-time systems
telephone switching systems |
0.0 | 1 | 1982 | Software Structure of No. 5 ESS-A Distributed Telephone Switching System · IEEE Trans. Commun. 1982 |
Methods — techniques the papers use, named apart from their topics
parallel decomposition · 0.0software engineering principles · 0.0token flow model · 0.0graph model · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1982 | Software Structure of No. 5 ESS-A Distributed Telephone Switching SystemabstractMost stored program controlled telephone switching systems are designed with centralized control architectures. Evolving processor technology and requirements of smooth growth over a wide size range have led system designers to take advantage of distributed processing architectures. This paper provides a conceptual framework for software partitioning on a distributed stored-program controlled switching system and discusses the resulting software structure as present in No. 5 ESS. To facilitate the software development process, a methodology based on current software engineering principles is employed. Sufficiently decoupled software components have expedited parallel development of software and provided reliability by reducing interaction and limiting propagation of errors among software components. The structuring strategy described for telephone switching is equally applicable to other distributed real-time control systems. Tom Duncan, Wing H. Huen |
IEEE Trans. Commun. | 2 |
| 1980 | Distributed Enumaration on Between ComputersabstractKnown solutions of a large number of important (and difficult) computational problems called NP-complete problems depend on enumeration techniques which examine all feasible alternatives. This paper considers the design of enumeration schemes in a distributed environment in an attempt to exploit the parallel activities inherent in enumeration algorithms. Ossama Ibrahim El-Dessouki, Wing H. Huen |
IEEE Trans. Computers | 2 |
| 1974 | Intermodule Protocol For Register Transfer Level Modules: Representation and Analytic ToolsabstractA distinguishing feature of modular design from ad hoc design is the establishment of an intermodule protocol to which all modules adhere. The problem of representing and analyzing intermodule protocol for the control portion of register transfer level systems is outlined. An introduction to two existing graph models of computation indicates that existing register transfer level module sets are representable by various "token flow" models. A single model that is capable of representing the token flow models and some of its analytical properties are illustrated by example. Finally, three examples of deadlocks in existing modules sets are presented. These deadlocks were uncovered by the analytic properties of the new model. One example is due to incorrect interconnection of modules at the user level. The other two illustrate incorrect signaling conventions between modules necessitating a redesign of some modules. Wing H. Huen, Daniel P. Siewiorek |
ISCA | 1 |