VLDB 2026 Research / reviewers in the wild / expert

Magesh Sadasivam

dblp:29/1747 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2004
—ORCID · unresolved

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 30% Memory systems · 30% Hardware accelerators and domain-specific architectures · 30%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
data-centric computing		 0.012004
Dynamically reconfigurable architecture for high-throughput processing of data centric applications · FPGA 2004
Reconfigurable computing and FPGAs
reconfigurable architecture		 0.012004
Dynamically reconfigurable architecture for high-throughput processing of data centric applications · FPGA 2004
Processor architecture and microarchitecture
pipelining		 0.012004
Dynamically reconfigurable architecture for high-throughput processing of data centric applications · FPGA 2004

Methods — techniques the papers use, named apart from their topics

two-level pipelining · 0.0static dataflow graph reconfiguration · 0.0
YearPublicationVenuePosition
2004 Dynamically reconfigurable architecture for high-throughput processing of data centric applications
abstract
This paper presents a reconfigurable platform for executing data centric applications. The proposed platform realizes applications where buffers are dominated in the design. Such characteristics of application domain is mostly exhibited by loop based processing systems. To increase the throughput, the platform is centered around buffers interacting through reconfigurable interconnect. Each buffer is associated with an autonomous reconfigurable controller where reconfiguration parameters are obtained statically from the dataflow graph. The execution concurrency is maintained by two level pipelining mechanism. We illustrate that the proposed platform is highly regular and decreases dynamic reconfiguration time significantly.
Magesh Sadasivam, Sangjin Hong
 FPGA1