When a nontrivial permutation of a Hermitian code is given, the code will have a module structure over a polynomial ring of one variable. By exploiting the theory of Gro/spl uml/bner bases for modules, a novel and elegant systematic encoding scheme for Hermitian codes is proposed by Heegard et al. (1995). The goal of this paper is to develop a serial-in-serial-out hardware architecture, similar to a classical cyclic encoder, for such a systematic encoding scheme. Moreover, we demonstrate that under a specific permutation, the upper bounds of the numbers of memory elements and constant multipliers in the proposed architecture are both proportional to O(n), where n is the length of the Hermitian code. To encode a codeword of length n, this architecture takes n clock cycles without any latency. Therefore, the hardware complexity of the proposed architecture is much less than that of the brute-force systematic encoding by matrix multiplication.

When a Hermitian curve is put in a special position with respect to its infinite rational point, the (x, y) coordinates of all its finite rational points have regular algebraic properties. Based on these properties, the use of Horner's rule and the mechanism of Chien search in the decoding of Reed-Solomon codes can be extended to render architectures for syndrome generation and error-location search in the decoding of codes constructed from the Hermitian curve.