Multi-tenant datacenters are successful because tenants can seamlessly port their applications and services to the cloud. Virtual Machine (VM) technology plays an integral role in this success by enabling a diverse set of software to be run on a unified underlying framework. This flexibility, however, comes at the cost of dealing with out-dated, inefficient, or misconfigured TCP stacks implemented in the VMs. This paper investigates if administrators can take control of a VM's TCP congestion control algorithm without making changes to the VM or network hardware. We propose AC/DC TCP, a scheme that exerts fine-grained control over arbitrary tenant TCP stacks by enforcing per-flow congestion control in the virtual switch (vSwitch). Our scheme is light-weight, flexible, scalable and can police non-conforming flows. In our evaluation the computational overhead of AC/DC TCP is less than one percentage point and we show implementing an administrator-defined congestion control algorithm in the vSwitch (i.e., DCTCP) closely tracks its native performance, regardless of the VM's TCP stack.

Datacenter networks deal with a variety of workloads, ranging from latency-sensitive small flows to bandwidth-hungry large flows. Load balancing schemes based on flow hashing, e.g., ECMP, cause congestion when hash collisions occur and can perform poorly in asymmetric topologies. Recent proposals to load balance the network require centralized traffic engineering, multipath-aware transport, or expensive specialized hardware. We propose a mechanism that avoids these limitations by (i) pushing load-balancing functionality into the soft network edge (e.g., virtual switches) such that no changes are required in the transport layer, customer VMs, or networking hardware, and (ii) load balancing on fine-grained, near-uniform units of data (flowcells) that fit within end-host segment offload optimizations used to support fast networking speeds. We design and implement such a soft-edge load balancing scheme, called Presto, and evaluate it on a 10 Gbps physical testbed. We demonstrate the computational impact of packet reordering on receivers and propose a mechanism to handle reordering in the TCP receive offload functionality. Presto's performance closely tracks that of a single, non-blocking switch over many workloads and is adaptive to failures and topology asymmetry.

The use of SOAP based communication protocol in complex Service-Oriented Architecture (SOA) environments can cause a significant strain on network resources thereby degrading application level performance. In this paper, we present software and hardware approaches for transparent line-rate encoding and decoding of SOAP traffic for alleviating network bandwidth bottlenecks. The proposed approaches are significantly lighter weight than gzip and binary XML encoding techniques while achieving better compression ratios. First we present a software-based scheme with a linear runtime that uses a finite set of pre-selected message templates for differential encoding of SOAP messages. We propose generating the templates by extracting the longest common subsequence from a representative set of SOAP messages encountered during the service operation. Next we present an architecture for line-rate implementation of data differencing functionality in hardware. As compared to the software-based scheme, the hardware design allows higher flexibility in the template selection and message encoding without compromising the encoder throughput. We test both schemes on a sample workload running on a SOAP based Business Intelligence software platform. Our results show that the proposed techniques can achieve an average of 10X reduction in the overall SOAP traffic. Furthermore, we show that the differentially encoded data can be further compressed by gzip to achieve a combined 15-17X reduction in the message sizes as compared to less than 5X compression obtained when using gzip by itself.

Software-defined networking introduces the possibility of building self-tuning networks that constantly monitor network conditions and react rapidly to important events such as congestion. Unfortunately, state-of-the-art monitoring mechanisms for conventional networks require hundreds of milliseconds to seconds to extract global network state, like link utilization or the identity of "elephant" flows. Such latencies are adequate for responding to persistent issues, e.g., link failures or long-lasting congestion, but are inadequate for responding to transient problems, e.g., congestion induced by bursty workloads sharing a link. In this paper, we present Planck, a novel network measurement architecture that employs oversubscribed port mirroring to extract network information at 280 µs--7 ms timescales on a 1 Gbps commodity switch and 275 µs--4 ms timescales on a 10 Gbps commodity switch,over 11x and 18x faster than recent approaches, respectively (and up to 291x if switch firmware allowed buffering to be disabled on some ports). To demonstrate the value of Planck's speed and accuracy, we use it to drive a traffic engineering application that can reroute congested flows in milliseconds. On a 10 Gbps commodity switch, Planck-driven traffic engineering achieves aggregate throughput within 1--4% of optimal for most workloads we evaluated, even with flows as small as 50 MiB, an improvement of up to 53% over previous schemes.

Dictionary matching is a commonly used operation in Information Extraction (IE) systems. It involves matching a set of strings in a document against a dictionary of pre-defined patterns. In this paper, we describe a high performance and scalable hardware architecture to enable high throughput dictionary matching on very large dictionaries for text analytics applications. Our hardware accelerator employs a novel hashing based approach instead of commonly used deterministic finite automata (DFA) based algorithms. A limitation of the DFA based approaches is that they typically process one character every cycle, while the proposed hash based scheme can process a string token every cycle, thus achieving significantly higher processing throughput than the DFA based implementations. Our measurement results based on a prototype implementation on an Altera Stratix IV FPGA device indicate that our hardware dictionary matching engine can process typical document streams at a processing rate of ~1.5GB/s (~12 Gbps) while simultaneously allowing support for large dictionary sizes containing up to ~100K patterns, thus making it very useful for IE workload acceleration.

The use of multiple-patterning (MP) optical lithography for sub-20 nm technologies has inevitably become slow to adopt the next generation of lithography systems. The biggest technical challenge of MP is failure to reach a manufacturable layout-coloring solution, especially in dense layouts. This paper offers a post layout solution for the removal of conflicts, i.e., patterns that cannot be assigned to different masks without violating spacing rules. The proposed method essentially consists of three steps: 1) layout coloring; 2) exposure layers; 3) geometric rules definition; and 4) layout legalization using compaction and MP rules as constraints. The method is general and can be used for different MP technologies, including lithography-etch, lithography-etch double-patterning (DP), triple patterning/MP (i.e., multiple litho-etch steps), and self-aligned DP (SADP). For demonstration purposes, we apply the proposed method in this paper to remove conflicts in DP. We offer anO(n) layout-coloring heuristic algorithm for DP, which is up to 80× faster than the integer linear program-based approach. The conflict-removal problem is formulated as a linear program, which permits an extremely fast runtime (less than 1 min in real time for macro layouts). The method was tested on standard cells and macro layouts from a commercial 22-nm library designed without any MP awareness. For many cells, the method removes all conflicts without any area increase. For some complex cells and macros, the method still removes all conflicts but with a modest 6% average increase in area.

Double patterning lithography (DPL) provides an attractive optical lithography solution for 32nm and subsequent technology nodes. There are two primary DPL techniques: pitch-split double patterning (PSDP) and self-aligned double patterning (SADP), which can be implemented using a positive tone or a negative tone process. Each DPL implementation has a different impact on line space and linewidth variation, and by analyzing the impact of these different DPL options the best overall process flow can be achieved. This paper presents a comprehensive analysis and optimization framework that compares the layerwise impact of different DPL choices on SRAM robustness, density, and printability. It then performs a sizing optimization that accounts for increased variability due to DPL for each layer. Experimental results based on 45nm industrial models show that using the best DPL option for each layer, along with the sizing optimization presented, we can achieve single exposure robustness together with improved DPL printability at almost no overhead (less than 0.2% increase in write energy). Specifically, cell failure probability can be further reduced by 5X as compared to the single exposure failure probability, at the cost of increasing write energy by 6.3% and write delay by 2.5%.

In the face of continued technology scaling with limited lithographic capabilities, there has been a push towards increased co-optimization of design and process. A key enabler is enhancing the design-manufacturing interface to allow more information than traditional layout shapes to propagate to lithography. We describe a method to generate this additional information in the form of shape tolerances on layout polygons. We further develop two different manufacturing methods to utilize these tolerances during mask optimization. One is a tolerance-driven optical proximity correction algorithm to limit on-wafer lithographic hotspots by constraining process window contours to lie within tolerances. The second is a layout optimization approach that modifies layout shapes during OPC to make them more robust to process variations. Our simulation results show that this increased level of interaction between design and lithography can lead to fewer process hotspots on-wafer compared to conventional design-oblivious methods.

Variations in delay caused by within-die and die-to-die process variations and SOI history effect increase timing margins and reduce performance. In order to develop mitigation techniques to reduce the detrimental effects of delay variations, particularly those that occur within-die, new methods of measuring delay variations within actual products are needed. The data provided by such techniques can also be used for validating models, i.e., can assist with model-to-hardware correlation. In this paper, we propose a flush delay technique for measuring both regional delay variations and SOI history effect and validate the method using a test structure fabricated in a 65 nm SOI process.

While the next generation of lithography systems is still under development, extending optical lithography using double patterning (DP) is the only solution to continue technology scaling. The biggest technical challenge of DP is the presence of mask-assignment conflicts in dense layers. In this paper, we propose a framework for DP conflict removal for standard cells. First, we offer an O(n) algorithm for mask assignment (up to 200× faster than the ILP-based approach) that guarantees a conflict-free solution if one exists. We then formulate the problem of conflict removal as a linear program (LP), which permits an extremely fast run-time (less than 10 seconds in real time for typical cells). The framework removes DP conflicts and legalizes the layout across all layers simultaneously while minimizing layout perturbation. For cells from a commercial 22nm library designed without any DP awareness, our method usually removes all DP conflicts without any area increase; for some complex cells, the method still removes all conflicts with a modest 6.7% average increase in area. The method is more general, however, and can also be applied for macro layouts and the interconnect layers in complete designs as we demonstrate in the paper.

We propose an efficient Hermite spline-based SPICE simulation methodology for accurate statistical yield analysis. Unlike conventional methods, the spline-based transistor tables are built on-demand specific to the transient simulation requirements of the statistical experiments. Compared with traditional MOSFET table models, on-demand spline table models use ~500X less memory. This makes Hermite spline-based table models practical for use in simulations for process variation modeling. Furthermore, we propose an efficient gate voltage offset approach to model transistor threshold voltage variation. In this scenario, evaluations of the transistor model rely on a single reference table and require one set of spline function evaluations per VTsample point as opposed to two or more sets for VTinterpolation. This method is comprehensive and the results are in excellent agreement with traditional BSIM-based simulations. Around 4X improvement in speed, which includes the table generation cost, could be further improved by employing other fast-SPICE techniques or parallelism. To the best of our knowledge, this is the first time such a methodology has been coupled with importance sampling techniques to study the yield of memory designs.

As feature printability becomes more challenging in advanced technology nodes, measuring and characterizing process variation effects on delay and power is becoming increasingly important. In this paper, we present two embedded test structures (ETS) for carrying out path delay measurement in actual product designs. Of the two structures proposed here, one is designed to be incorporated into a customer's scan structures, augmenting selected functional units with the ability to perform accurate path delay measurements. We refer to this ETS as REBEL (regional delay behavior). It is designed to leverage the existing scan chain as a means of reducing area overhead and performance impact. For cases in which very high resolution of delay measurements is required, a second standalone structure is proposed which we refer to as TDC for time-to-digital converter. Beyond characterizing process variations, these ETSs can also be used for design debug, detection of hardware Trojans and small delay defects and as physical unclonable functions.

Suppresing device leakage while maximizing drive current is the prime focus of semiconductor industry. Rapid Thermal Annealing (RTA) drives process development on this front by enabling fabrication steps such as shallow juction formation that require a low thermal budget. However, decrease in junction anneal time for more aggressive device scaling has reduced the characteristic thermal length to dimensions less than the typical die size. Also, the amount of heat transferred, and hence the local anneal temperature, is affected by the layout pattern dependence of optical properties in a region. This variation in local anneal temperature causes a variation in performance and leakage across the chip by affecting the threshold voltage (Vth) and extrinsic transistor resistance (Rext). In this work, we propose a new local anneal temperature variation aware analysis framework which incorporates the effect of RTA induced temperature variation into timing and leakage analysis. We solve for chip level anneal temperature distribution, and employ TCAD based device level models for drive current (Ion) and leakage current (Ioff) dependence on anneal temperature variation, to capture the variation in device performance and leakage based on its position in the layout. Experimental results based on a 45 nm experimental test chip show anneal temperature variation of up to ~10.5°C, which results in ~6.8% variation in device performance and ~2.45X variation in device leakage across the chip. The corresponding variation in inverter delay was found to be ~7.3%. The temperature variation for a 65 nm test chip was found to be ~8.65°C.

Double Dipole Lithography (DDL) uses a combination of X and Y dipole exposures to achieve extreme off-axis illumination for both vertical and horizontal orientations. DDL requires decomposition of a given layout into two set of patterns for the respective dipole exposures. In this work, we propose a frequency domain decomposition flow for DDL. Our experiments show that the proposed frequency domain method not only eliminates the inherent ambiguity of the spatial rule-based flows but it also produces contours that exhibit significantly improved pattern fidelity across lithographic dose and focus variation.

Modern CMOS technologies employ process-induced stress to improve carrier mobility and increase drive current. This stress has been shown to be strongly layout dependent; however there is a lack of physical models relating potential performance variation to critical layout parameters. This paper presents compact closed-form models that capture the layout dependence of mechanical stress induced in the device channel while considering all relevant sources of stress (STI, tensile/compressive nitride liners, and embedded SiGe). The models are calibrated using ring oscillator frequency data obtained from an experimental test chip to verify their accuracy. Results indicate that the models accurately capture the layout dependence of stress and carrier mobility for a variety of layout permutations and the root mean square error in the predicted ring oscillator frequency is less than 1% for the different layout experiments. These models can help drive layout optimization and timing/power analysis without the use of technology computer-aided design (TCAD) tools, which are slow and very limited in capacity.

The move to low-k1 lithography makes it increasingly difficult to print feature sizes which are a small fraction of the wavelength of light. Manufacturing processes currently treat a target layout as a fixed requirement for lithography. However, in reality layout features may vary within certain bounds without violating design constraints. The knowledge of such tolerances, coupled with models for process variability, can help improve the manufacturability of layout features while still meeting design requirements. In this paper, we propose a methodology to convert electrical slack in a design to shape slack or tolerances on individual layout shapes using a two-phase approach. In the first step, we redistribute delay slack to generate delay bounds on individual cells using linear programming. In the second phase, which is solved as a quadratic program, we convert these delay bounds to shape tolerances to maximize the process window of each shape. The shape tolerances produced by our methodology can be used within a process-window optical proximity correction (PWOPC) flow to reduce delay errors arising from variations in the lithographic process. Our experiments on 45 nm SOI cells using accurate process models show that the use of our shape slack generation in conjunction with PWOPC reduces delay errors from 3.6% to 1.4%, on average, compared to the simplistic way of tolerance band generation.

We present compact on-die variation monitoring circuits for measuring process and environmental fluctuations in product chips. The process characterization structure can be used to isolate process induced systematic and random variation in NFET and PFET devices. The environmental monitoring structure is designed for real time monitoring of performance variations. The proposed structures provide an efficient trade-off between test cost and measurement data. The simulation results demonstrate that the proposed sensors show very good sensitivity to FET level threshold voltage and supply voltage fluctuations, respectively. Due to their low overhead and improved monitoring capabilities, the structures can be very effective as on-die embedded sensors for measuring spatial and temporal variability in integrated circuits.

Low-k1 lithography results in features that suffer from poor lithographic yield in the presence of process variation. The problem is especially pronounced for lower level metals used for local routing, where bi-directionality gives rise to lithography unfriendly layout patterns. However, one can modify such wires without significantly affecting design behavior. In this paper, we propose to simultaneously modify mask and target during OPC to improve lithographic yield. The method uses image slope information, available during image simulation at no extra cost, as a measure of process window. We derive a cost function that maximizes both contour fidelity and robustness to drive our simultaneous mask and target optimization (SMATO) method. We then develop analytical equations to predict the cost for a given mask and target modification and use a fast algorithm to minimize this cost function to obtain an optimal mask and target solution. Our experiments on sample metal1 (M1) layouts show that the use of SMATO reduces the Process Manufacturability Index (PMI) by 15.4% compared to OPC, which further leads to 69% reduction in the number of layout hotspots. Additionally, such improvement is obtained at low average runtime overhead (5.5%). Compared to PWOPC, we observe 4.6% improvement in PMI at large (2.6X) improvement in runtime.

Double patterning lithography (DPL) is widely considered the only lithography solution for 32nm and several subsequent technology nodes. DPL decomposes and prints the critical layout shapes in two exposures, leading to mismatch between adjacent devices due to systematic offsets between the two exposures. This results in adjacent devices with different mean critical dimension (CD), and uncorrelated CD variation. Such a mismatch can increase functional failures in SRAM cells and degrade yield. This paper analyzes the impact of DPL on functional failures in SRAM bitcells, and proposes a DPL-aware SRAM sizing scheme to effectively mitigate yield losses. Experimental results based on 45nm industrial models and test chip measurements show that DPL can significantly impact SRAM cell robustness. Using the proposed DPL-aware sizing scheme, the SRAM cell failure probability can be reduced by up to 3.6X. Also, for iso-robustness, cells optimized by the proposed approach have 7.9% lower dynamic energy as compared to non-DPL aware sizing optimization.

Traditional process variation modeling is primarily focused on design-time analysis and optimization. However, with the advances of post-silicon techniques, accurate variation model is also highly desired in various post-silicon applications, such as post-silicon tuning, test vector generation, and reliability prediction. The accuracy of such post-silicon variation models is greatly improved by incorporating test measurements from each wafer or die. However, to limit test cost, the number of measurements must be reduced as much as possible. This paper proposes an active learning framework to dynamically extract post-silicon process variation models with tightened variance from measurements. The framework is composed of two stages, active training and model adaptation. Active training collects information and initializes the models to be used for the forthcoming wafers. Model adaptation stage then validates the models and optimally determines the test configuration for partial testing to reduce the test cost. Experimental results based on the measurements from two industrial processes show that the proposed framework can achieve variation models with variance reduction of ~80% when compared with design-time variation models. Meanwhile, the average estimation error for those untested sites is well maintained at ~2-3% using merely ~30% available test structures for two processes.

Embedded test structures are increasingly being used to measure and analyze performance and power variations in product chips to better understand the impact of process variations. In this work, we propose a minimally-invasive, low-overhead technique for characterizing within-die and die-to-die leakage variation. The proposed technique leverages existing power control circuitry added by designers to reduce the power consumption of inactive functional units. We manipulate these `sleep islands' to isolate and measure their leakage current contribution to the chip-wide leakage current. The measured set of sleep island leakage currents reflect the leakage current variation across the chip at a coarse level of resolution. In order to improve resolution, we propose a multiple power supply port (MSP) measurement technique to provide `within-island' leakage current measurements. A calibration technique is described that corrects for differences between the sleep island and MSP approaches, effectively enabling the same information to be obtained using either technique. We demonstrate the techniques on a set of test chips fabricated in 65-nm SOI technology. The results show that leakage current variations across a small test structure array have both a locally random and globally deterministic component that can be accurately mapped using the sleep island or MSP approaches.

Process-induced mechanical stress is used to enhance carrier transport and achieve higher drive currents in current complementary metal-oxide-semiconductor technologies. This paper explores how to fully exploit the layout dependence of stress enhancement and proposes a circuit-level, block-based, stress-enhanced optimization algorithm that uses stress-optimized layouts in conjunction with dual-Vthassignment to achieve optimal power-performance tradeoffs. We begin by studying how channel stress and drive current depend on layout parameters such as active area length and contact placement, while considering all layout-dependent sources of mechanical stress in a 65 nm industrial process. We then investigate the three main layout properties that impact mechanical stress in this process and discuss how to improve stress-based performance enhancement in standard cell libraries. While varying the stress-altering layout properties of a number of standard cells in a 65 nm industrial library, we show that ?dual-stress? standard cell layouts (analogous to ?dual-Vth?) can be designed to achieve drive current differences up to ~ 14% while incurring less than half the leakage penalty of dual-Vth. Therefore, when the flexibility of ?dual-stress? assignment is combined with dual-Vthassignment (within the proposed joint optimization framework), simulation results for a set of benchmark circuits show that leakage is reduced by ~ 24% on average, for iso-delay, when compared to dual-Vthassignment. Since mobility enhancement does not incur the exponential leakage penalty associated withVthassignment, our optimization technique is ideal for leakage power reduction. However, our framework can also be used to achieve higher performance circuits for iso-leakage and our joint optimization framework can be used to reduce delay on average by ~ 5%. In both cases, the proposed method only incurs a small area penalty (<0.5%).

Increased buffer insertion along on-chip global lines and growing amounts of leakage power have resulted in buffer-based leakage emerging as one of the chief contributors to system leakage power. In this paper, a bus system prototype is implemented in an industrial 65-nm SOI technology and measured results show up to a 45% reduction in total bus system power and an average reduction of 2.4× in standby mode leakage power.

The importance of within-die process variation and its impact on product yield has increased significantly with scaling. Within-die variation is typically monitored by embedding characterization circuits in product chips. In this work, we propose a minimally-invasive, low-overhead technique for characterizing within-die variation. The proposed technique monitors within-die variation by measuring quiescent (IDDQ) currents at multiple power supply ports during wafer-probe test. We show that the spatially distributed nature of power ports enables spatial observation of process variation. We demonstrate our methodology on an experimental test-chip fabricated in 65-nm technology. The measurement results show that the IDDQ currents drawn by multiple power supply ports correlate very well with the variation trends introduced by state-dependent leakage patterns.

In recent years, process-induced mechanical stress has emerged as a useful manufacturing technique that enhances carrier transport and increases drive currents. This improvement in current has helped to compensate the decline of device scaling factors in parameters such as tox, Vth, and Vdd. In this work, we propose stress as a means to achieve optimal power-performance trade-off by combining stress-based, performance-enhanced standard cell assignment with dual-Vth assignment. We study how stress-induced performance enhancements are affected by layout properties and improve standard cell layouts so that performance gains are maximized. We then develop a circuit-level, block-based, stress-enhanced optimization algorithm that includes all layout-dependent sources of mechanical stress. By combining the two performance enhancement techniques (stress-based and dual-Vth) for a set of benchmark circuits, we find that our stress-aware optimization, decreases leakage by ~24% on average, for iso-delay, when compared to dual-Vth assignment. Similarly, for iso-leakage, our optimization algorithm reduces delay on average by 5%. In both cases, the proposed method only incurs a small area penalty (< 0.5%).

Process-induced mechanical stress is used to enhance carrier transport and achieve higher drive currents in current CMOS technologies. In this paper, we study how stress-induced performance enhancements are affected by layout properties and suggest guidelines for improving layouts so that performance gains are maximized. All MOS devices in this work include STI and nitride stress liners as sources of stress. Additionally, the PMOS devices incorporate the stress effects caused by the embedded SiGe S/D layer common in today's processes. First, we study how stress and drive current depend on layout parameters such as active area length and contact placement. We develop an intuition for the drive current dependency on these parameters and propose simple guidelines to improve a layout while considering mechanical stress effects. We then use these guidelines to improve the standard cell layouts in a 65nm industrial library. Experimental results show that we can enhance NMOS and PMOS drive currents by ~5% and ~12%, respectively, while only increasing NMOS leakage current by 1.48X and PMOS leakage current by 3.78X. By applying our guidelines to a 3-input NOR gate and a 3-input NAND gate, we are able to achieve a ~13.5% PMOS drive current improvement in the NOR gate and a ~7% NMOS drive current improvement in the NAND gate, without increasing cell area in either case

The impact of process variation on SRAM yield has become a serious concern in scaled technologies. In this paper, we propose a methodology to analyze the stability of an SRAM cell in the presence of random fluctuations in the device parameters. First, we develop a theoretical framework for characterizing the dc noise margin of a memory cell. The framework is based on the concept that an SRAM cell is on the verge of instability when the gain across the loop formed by the cross-coupled inverters in the cell is unity. The noise margin criteria developed in this manner can be used to verify a cell stability in the presence of arbitrary DC noise offsets at the two storage nodes in the cell. We also develop metrics for estimating the cell stability during read and write operations and verify these models by extensive Monte Carlo simulations in a 65-nm CMOS process. Our results show that the proposed robustness metrics can be used to estimate cell failure probabilities in an efficient and accurate manner.

The correlation of a statistical analysis tool to hardware depends on the accuracy of underlying variation models. The models should represent actual process behavior as measured in silicon. In this paper, we present an overview of test structures for characterizing statistical variation of process parameters. We discuss the test structure design and characterization strategy for calibrating random and layout dependent systematic components of process variation. We also show measurement results from several fabricated structures in 65-nm CMOS technologies.

Electromigration(EM) andself-heatingare critical reliability concerns for metal wires in high performance designs. EM reliability rules for a VLSI technology are typically expressed in terms of average, root-mean-square and peak current limits for each metal layer in the technology. To ensure EM reliability of a design, current flowing through each wire segment in the design should not violate the EM reliability rules. In this work, we present closed-from analytical models for efficient computation of average, root-mean-square and peak currents through any element in an arbitrary RC tree. The proposed models are validated against SPICE simulations for several RC nets extracted from an industrial ASIC design. The results show that the models exhibit very good accuracy with a mean error of only 3.1% in root-mean-square and 0.2% in average current estimation.

Parametric yield loss has become a serious concern in nanometer technologies. In this paper, we propose a methodology to estimate and optimize the parametric yield of a design in the presence of process variations. We discuss the impact of leakage on parametric yield given that leakage causes the parametric yield window to shrink by imposing a two-sided constraint in conjunction with performance targets on the yield window. We present a mathematical framework for yield estimation under process variation for a given power and frequency constraints. The model is validated against Monte Carlo SPICE simulations in a 90-nm CMOS process and is shown to have a typical error of less than 5%. We then demonstrate the importance of optimal supply and threshold voltage selection for yield maximization. Our results show that parametric yield is highly sensitive to supply voltage with only a 5% change in the supply voltage potentially leading to nearly 15% yield degradation. We also investigate the sensitivity of parametric yield to required frequency and power constraints. Finally, we apply the proposed framework to the problem of maximizing the shipping frequency in the presence of given yield and power constraints.

The exponential increase in leakage power due to technology scaling has made power gating an attractive design choice for low-power applications. In this paper, we explore this design style in large combinational circuit blocks and latch-to-latch datapaths and introduce a novel power gating approach to yield an improved power-performance tradeoff. We first present a multiple sleep mode power gating technique where each mode represents a different point in the wake-up overhead versus leakage savings design space. We show that the high wake-up latency and wake-up power penalty of traditional power gating limits its application to large stretches of inactivity. The multiple-mode feature allows a processor to enter power saving modes more frequently, hence, resulting in enhanced leakage savings. We apply the multimode power gating technique to datapaths where the degree of applied power gating becomes progressively stronger (harder) along the datapath. This configuration allows us to further balance wake-up overhead with leakage savings by exploiting the fact that logic circuits deep in the datapath have higher wakeup margin and hence can be strongly gated. Simulations show that multiple sleep mode capability provides an extra 17% reduction in overall leakage compared to traditional single mode gating. The multiple modes can be designed to allow state-retentive modes. The results on benchmarks show that a single state-retentive mode can reduce leakage by 19% while preserving state of the circuit.

The impact of process variation on SRAM yield has become a serious concern in scaled technologies. In this paper, we propose a methodology to analyze the stability of an SRAM cell in the presence of random fluctuations in the device parameters. We provide a theoretical framework for characterizing the DC noise margin of a memory cell and develop models for estimating the cell failure probabilities during read and write operations. The proposed models are verified against extensive Monte-Carlo simulations and are shown to match well over the entire range of the distributions well beyond the 3-sigma extreme.

Leakage is an important performance bottleneck in current digital integrated circuit technology. Many techniques were proposed to analyze, control and avoid leakage of a circuit, but all efforts need accurate characterizations of total leakage variations of a chip under real-life manufacturing and environmental parameter fluctuations. In this paper, we are proposing to apply a new statistical technique to model the overall distribution of total chip leakage under such variations. With our proposed model, chip designers and design automation tools can better assess and manage leakage power

Technology scaling and the push for ever increased performance has resulted in the rapid increase of integrated circuit power dissipation. We are already in the era of the 100 Watt IC (Diefendorff, 1999). This necessitates the detailed modeling and analysis of the on-chip power distribution for robustness and reliability (Chen and Ling, 1997). An important component of this model is the decoupling capacitance of the design which includes dedicated decoupling capacitors as well as the capacitance of non-switching circuits. This paper describes a technique for modeling the decoupling capacitance of circuits. An exact simulation-based method is outlined, and fast yet accurate analytical models are proposed

In this paper, statistical models for the efficient analysis of interconnect delay and crosstalk noise in the presence of back-end process variations are developed. The proposed models enable closed-form computation of means and variances of interconnect-delay, crosstalk-noise peak, and coupling-induced-delay change for given magnitudes of variation in relevant process parameters, such as linewidth, metal thickness, metal spacing, and interlayer dielectric (ILD) thickness. The proposed approach is based on the observation that if the variations in different physical dimensions are assumed to be independent normal random variables, then the interconnect behavior also tends to have a Gaussian distribution. In the proposed statistical models, delay and noise are expressed directly as functions of changes in physical parameters. This formulation allows us to preserve all correlations and can be very useful in evaluating delay and noise sensitivities due to changes in various physical dimensions. For interconnect-delay computation, the authors express the resistance and capacitance of a line as a linear function of random variables and then use these to compute circuit moments. They show that ignoring higher order terms in the resulting variational moments does not result in a loss of accuracy. Finally, these variability-aware moments are used in known closed-form delay and slew metrics to compute interconnect-delay probability density functions (pdfs). Similarly for coupling noise and dynamic-delay analysis, the authors rely on the linearity (Gaussian) assumption, allowing us to truncate nonlinear terms and express noise and dynamic-delay pdfs as linear functions of variations in relevant geometric dimensions. They compare their approach to SPICE-based Monte Carlo simulations and report the error in mean and standard deviation of interconnect delay to be 1% and 4% on average, respectively

At current operating frequencies, inductive-coupling effects can be significant and should be included for accurate crosstalk-noise analysis. In this paper, an analytical framework to model crosstalk noise in coupled RLC interconnects is presented. The proposed model is based on transmission-line theory and captures high-frequency effects in on-chip interconnects. The new model is generic in nature and can be applied to asymmetric driver-and-line configurations for aggressor and victim wires. The model is compared against SPICE simulations and is shown to capture both the waveform shape and peak noise accurately. Over a large set of random test cases, the average error in noise-peak estimation is approximately 6.5%. A key feature of the new model is that its derivation and form enables physical insight into the total coupling-noise-waveform shape and its dependence on relevant physical-design parameters. Due to its simplicity and physical nature, the proposed model can be applied to investigate the impact of various physical-design optimizations (e.g., wire sizing and spacing, shield insertion) on total RLC coupled noise. The effectiveness of various existing noise-reduction techniques in the presence of mutual-inductance coupling is studied here. The obtained results indicate that common (capacitive) noise-avoidance techniques can behave quite differently when both capacitive and inductive coupling are considered together.

In this paper, we develop an approach for statistical modeling of crosstalk noise and dynamic delay degradation in coupled RC interconnects under process variations. The proposed model enables closed-form computation of mean and variance of noise peak and worst case dynamic delay for given variabilities in physical dimensions. We compare the proposed model against HSPICE Monte Carlo simulations and report an average error in mean and standard deviation of noise peak to be 2.7% and 3.7% respectively.

In this paper, we present a novel approach to obtain any desired intermediate threshold voltage in a dual VT process. The intermediate threshold voltages are achieved by combining low and high threshold voltages in a device. We show that this combination can be easily implemented in layouts with negligible design and manufacturing overhead. Our results show that power-delay characteristics of the achieved intermediate thresholds match well with the ideal (but impractical) scenario that assumes that all intermediate thresholds are available in the technology.

Increasing levels of process variation in current technologies have a major impact on power and performance, and result in parametric yield loss. In this work we develop an efficient gate-level approach to accurately estimate the parametric yield defined by leakage power and delay constraints, by finding the joint probability distribution function (jpdf) for delay and leakage power. We consider inter-die variations as well as intra-die variations with correlated and random components. The correlation between power and performance arise due to their dependence on common process parameters and is shown to have a significant impact on yield in high-frequency bins. We also propose a method to estimate parametric yield given the power/delay jpdf that is much faster than numerical integration with good accuracy. The proposed approach is implemented and compared with Monte Carlo simulations and shows high accuracy, with the yield estimates achieving an average error of 2%.

In this paper we develop an approach to model interconnect delay under process variability for timing analysis and physical design optimization. The technique allows for closed-form computation of interconnect delay probability density functions (PDFs) given variations in relevant process parameters such as linewidth, metal thickness, and dielectric thickness. We express the resistance and capacitance of a line as a linear function of random variables and then use these to compute circuit moments. Finally, these variability-aware moments are used in known closed-form delay metrics to compute interconnect delay PDFs. We compare the approach to SPICE based Monte Carlo simulations and report an error in mean and standard deviation of delay of 1% and 4% on average, respectively.

High performance digital circuits require long bus lines to operate at very high frequencies, necessitating a large number of repeaters to be inserted along these lines. Power consumed by repeaters, particularly that contributed by subthreshold leakage, is becoming a major consideration in digital design. We compare several threshold voltage assignment schemes to reduce runtime leakage power in buffers. We explore trade-offs between dynamic and static power by selectively mixing high and low Vt devices within a pull-up or pull-down network. We propose an activity-dependent hybrid Vt assignment scheme that can be applied across a bus. These configurations are shown to reduce total power by up to 38% and runtime leakage by up to 48%, with negligible design or area overhead.

In this paper, we present various design approaches to leakage minimization in global repeaters. We demonstrate the applicability of the MTCMOS scheme to global repeaters for leakage reduction. We then analyze two design approaches called Duplicated Skewed Buses and Skewed Pulsed Buses. We show that significant reduction in standby leakage power can be obtained using these approaches while providing significant improvements in performance. We also illustrate the use of these proposed techniques with the MTCMOS approach to obtain further savings in leakage power. Simulations results in a 90nm process show that skewed pulsed buses with MTCMOS can provide 20% improvement in performance with over 25% reduction in active mode leakage and nearly 100X reduction in standby mode leakage.

This paper presents a new library-compatible approach to gate-level timing characterization in the presence of resistive/inductive/capacitive (RLC) interconnect loads. We show that for a gate driving an RLC interconnect, the driver-output waveform exhibits inflection points and, hence, the traditional approach of approximating driver output with a saturated ramp is highly inaccurate. We describe a two-ramp model based on transmission-line theory that accurately predicts both the 50% delay and waveform shape (slew rate) at the driver output when inductive effects are significant. The approach does not rely on piecewise linear Thevenin voltage sources and is compatible with existing library characterization methods. Results are compared with SPICE and demonstrate typical errors under 10% for both delay and slew rate. We also propose a new criterion for evaluating the importance of on-chip inductance by comparing rise time at the driver output with the time of flight.

In this paper, we introduce a simple metric for the slew rate of an RC circuit based on the first two circuit moments. Metrics focusing on 50% delay of RC circuits have been proposed recently that greatly improve the accuracy of the traditional Elmore delay model. However, these new models have not been applied to the determination of transition time or slew rates (e.g., 10-90% of V/sub dd/). We study how well existing approaches to 50% delay modeling translate to slew-rate modeling. We first describe a new metric called slew with two moments (S2M) that is based on Elmore's observation that the transition time of a step response is proportional to the standard deviation of the corresponding impulse response. The S2M metric modifies Elmore's original formulation by deriving a new constant of proportionality. This new constant is shown to be more accurate for general RC circuits. Next, we show that metrics relying on a simple constant multiplied by standard deviation such as S2M and Elmore do not work well for near-end nodes. To address this issue, we propose a new slew metric called scaled S2M that provides high accuracy across all types of nodes, while maintaining the advantage of a simple closed-form expression. Scaled S2M is shown to be very accurate for both near and far-end nodes. The average error for scaled S2M is approximately 2% with 96% of all nodes showing less than 5% error from a large set of industrial 0.18-/spl mu/m microprocessor nets.

ABSTRACT * This paper presents a new library compatible approach to gatelevel timing characterization in the presence of RLC interconnect loads. We describe a two-ramp model based on transmission line theory that accurately predicts both the 50 % delay and waveform shape (slew rate) at the driver output when inductive effects are significant. The approach does not rely on piecewise linear Thevenin voltage sources. It is compatible with existing library characterization methods and is computationally efficient. Results are compared with SPICE and demonstrate typical errors under 10 % for both delay and slew rate. Categories and Subject Descriptors

In this paper we introduce simple metrics for the slew rate of an RC circuit based on the first two circuit moments. We develop two new slew metrics, S2M (slew with 2 moments) and scaled S2M, that provide high accuracy with the advantage of simple closed form expressions. S2M is very accurate for middle and far end nodes but it does not perform as well for near end nodes. Scaled S2M is developed to improve upon S2M for near end nodes and is shown to be highly accurate for near as well as far end nodes. For a large set of nets from an industrial 0.18 μm microprocessor, S2M matches SPICE within 2% on average with 78% of the sinks having less than 1% error. For the same test cases, the average error for scaled S2M is less than 3% with 99.4% of the nodes showing less than 5% error.

We propose the concept of an optimal inductance value that can substantially reduce delay of global RLC signals while maintaining good signal integrity (low ringing/overshoot). We exploit the fact that inductance results in faster transition times to improve delay of buffers in global signal lines. We observe that voltage overshoot, slew rate, and total line delay all show strong inflection points at the same value of inductance. At this optimal value of inductance significant improvements in signal transition time, and hence in overall signal delay, are obtained with negligible ringing. We propose adjusting the power grid to achieve this optimal inductance. Results show that the delay of a I cm line with 9 inserted repeaters can be reduced by 8-12% with acceptable ringing by operating at the optimal inductance point.

A novel concept of bidirectional transformation between on-chip coupling noise waveform and delay-change curve (DCC) using closed-form equations is described in this paper. These equations are targeted for use in: 1) the efficient generation of DCCs and 2) accurate experimental determination of subnanosecond coupling noise. In particular, we explore the concept of using analytical models to efficiently generate DCCs that can then be used to characterize the impact of noise on any victim/aggressor configuration. The concept is model independent, although we investigate several common noise modeling choices and perform a sensitivity analysis to optimize the generation of DCCs. By extending existing noise models, arbitrary configurations can be considered including multiple aggressors in the timing-analysis framework. Simulation using the analytical approach closely matches time-consuming SPICE simulations, making noise-aware timing analysis using DCCs both efficient and accurate. A test chip using a 0.25-/spl mu/m CMOS process was designed and its measurement results also show good agreement with SPICE simulations.