Designing of arbiters has become increasingly important because of their wide use in such as multi-processor system-on-a-chips (MPSoCs) and on- or off- chip high-speed cross-bar switches and networks. In this and an accompanying paper [6], we proposed a new systematic model-driven flow for design of the proposed new scalable multi-facet arbiters through a 3-phase process combined with the template-based modular design approach: the design model derivation phase, the architecture model (or template) design phase as well as arbiter hardware implementation and generation phase. Here, we described the phase 1 of the design flow of how to induce an arbiter design model in detail by careful analysis of arbiter design issues and systematic design space exploring the construction of the model. Then, we continue to discuss the phase 2 of how to derive an architecture model or template using the reusability, modularity and expansibility techniques. With both the design and architecture models, designers can easily design or at least understand and thus choose many kinds of different but better arbiters efficiently. The phase 3 is described in the accompanying paper [6]. To our knowledge, this is the first time that such a systematic model-driven design approach is proposed for the practical hardware design.

An embedded in-circuit emulator (EICE) is an ICE embedded in the macro-controllers' core such that the ICE functions can be applied to test the chip after manufacturing. By incorporating the IEEE 1149.1 JTAG facilities, the ICE needs not additional pins. In this paper, we present an EICE generator to create an EICE in Verilog HDL specification that is re-targetable to different user-defined processor an re-configurable to different user-defined EICE functions with better performance and lower cost. For real-time tracing, users can specify which part of program execution to be traced and which part of data memory, and/or which part of the register file to be traced also. For non-real-time tracing, user can be set processor to operate in three modes: run to breakpoint mode, single step mode, run to stop mode. The Verilog program of EICE and the micro-controller are synthesized and mapped to Xilinx's FPGA for verification or for being used at board developing stage.

Calibration for servomotors is widely applied in various fields, especially in robot control and factory automation. Because the real time response to system control feedbacks is a compulsory characteristic for calibration for servomotor, a hardware structure with quick response characteristic needs to be implemented to replace the software. The goal is to prevent the servomotors from out of control. In this paper, a calibration control feedbacks system with remote monitoring features and parametric designs can be built rapidly through FPGA. Users can configure the number of axis and proportional integration derivative (PID) parameters by themselves with any other servomotors. Using Internet or LAN to realize the remote calibration control for servomotor system is also achievable.

In this paper, we propose a soft IP generator which can add or remove PCM codec modules arbitrarily. It can be applied to PCM codec IP designs that need to change their related modules, corresponding to different working environments. It also can help us to easily manage our soft IP modules, produce optimized modules, and remove unnecessary modules, in order to reduce the implementation cost. In addition, users can implement their own Verilog HDL code of PCM codec by following our predefined interface specification, and integrate it with our optimal PCM codec module to produce the users' own optimized system.

We present a new technique to synthesize high throughput pipelined data paths for those algorithms containing nested loops. Given an initiation interval constraint, the objective is to synthesize a low cost data path for the problem in register transfer level (RTL). Mapping algorithms for processor array synthesis which do not take initiation interval into account cannot be applied to our case; while traditional pipeline synthesis techniques suffer from complex interconnection and high register cost. Our contributions include proposing (1) an approach which conserves the regularities of nested loops, and (2) an architecture which possesses the advantages of both the highly multiplexed and lowly multiplexed architecture styles. Experiments on several algorithms in the image and DSP applications show this approach is very efficient.