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Zhuo Chen 0044

dblp:29/6497-44 · DBLP profile ↗
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2ranked-venue papers
1as first author
2since 2021 · last 2026
0009-0004-8038-4039ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Emerging computing paradigms · 78% Hardware accelerators and domain-specific architectures · 18% Interconnection networks and networks-on-chip · 4%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Emerging computing paradigms
neuromorphic computing
1.922026
DepAsync: An Asynchronous SNN Accelerator Based on Core-Dependency · IEEE Trans. Computers 2026
Mapping Large-Scale Spiking Neural Network on Arbitrary Meshed Neuromorphic Hardware · IEEE Trans. Parallel Distributed Syst. 2025
Emerging computing paradigms
neuromorphic hardware
1.922026
DepAsync: An Asynchronous SNN Accelerator Based on Core-Dependency · IEEE Trans. Computers 2026
Mapping Large-Scale Spiking Neural Network on Arbitrary Meshed Neuromorphic Hardware · IEEE Trans. Parallel Distributed Syst. 2025
Emerging computing paradigms › neuromorphic hardware
asynchronous neuromorphic hardware
1.012026
DepAsync: An Asynchronous SNN Accelerator Based on Core-Dependency · IEEE Trans. Computers 2026
Hardware accelerators and domain-specific architectures › machine learning accelerator › neural network accelerator
spiking neural network accelerator
1.012026
DepAsync: An Asynchronous SNN Accelerator Based on Core-Dependency · IEEE Trans. Computers 2026
Emerging computing paradigms › neuromorphic computing
spiking neural network
0.912025
Mapping Large-Scale Spiking Neural Network on Arbitrary Meshed Neuromorphic Hardware · IEEE Trans. Parallel Distributed Syst. 2025
Hardware accelerators and domain-specific architectures
many-core accelerator
0.312026
DepAsync: An Asynchronous SNN Accelerator Based on Core-Dependency · IEEE Trans. Computers 2026
Interconnection networks and networks-on-chip
network topology
0.312025
Mapping Large-Scale Spiking Neural Network on Arbitrary Meshed Neuromorphic Hardware · IEEE Trans. Parallel Distributed Syst. 2025

Methods — techniques the papers use, named apart from their topics

dependency-based scheduling · 1.0compile-time dependency analysis · 1.0space-filling curves · 0.9divide-and-conquer · 0.9
YearPublicationVenuePosition
2026 DepAsync: An Asynchronous SNN Accelerator Based on Core-Dependency
abstract
Spiking Neural Networks (SNNs) are widely used in brain-inspired computing and neuroscience research. Several many-core accelerators have been built to improve the running speed and energy efficiency of SNNs. However, current accelerators generally need explicit synchronization among all cores after each timestep of SNNs, which poses a challenge to overall efficiency. This paper proposes DepAsync, an asynchronous architecture that eliminates inter-core synchronization, facilitating fast and energy-efficient SNN inference with commendable scalability. The main idea is to exploit the dependency of neuromorphic cores predetermined at compile time. We design a DepAsync scheduler for each core to trace the running state of its dependencies and control the core to safely forward to the next timestep without waiting for other cores to complete their tasks. This approach prevents the necessity for global synchronization, allowing DepAsync to minimize core waiting time facing inherent core and time imbalance in SNN workloads. The comprehensive evaluations using five SNN workloads show that DepAsync achieves 2.47x speedup and 1.55x energy efficiency compared to the state-of-the-art synchronization architectures.
Zhuo Chen 0044, De Ma, Xiaofei Jin, Qinghui Xing, Ouwen Jin, Xin Du 0002, Shuibing He, Gang Pan 0001
IEEE Trans. Computers1
2025 Mapping Large-Scale Spiking Neural Network on Arbitrary Meshed Neuromorphic Hardware
abstract
Neuromorphic hardware systems—designed as 2D-mesh structures with parallel neurosynaptic cores—have proven highly efficient at executing large-scale spiking neural networks (SNNs). A critical challenge, however, lies in mapping neurons efficiently to these cores. While existing approaches work well with regular, fully functional mesh structures, they falter in real-world scenarios where hardware has irregular shapes or non-functional cores caused by defects or resource fragmentation. To address these limitations, we propose a novel mapping method based on an innovative space-filling curve: the Adaptive Locality-Preserving (ALP) curve. Using a unique divide-and-conquer construction algorithm, the ALP curve ensures adaptability to meshes of any shape while maintaining crucial locality properties—essential for efficient mapping. Our method demonstrates exceptional computational efficiency, making it ideal for large-scale deployments. These distinctive characteristics enable our approach to handle complex scenarios that challenge conventional methods. Experimental results show that our method matches state-of-the-art solutions in regular-shape mapping while achieving significant improvements in irregular scenarios, reducing communication overhead by up to 57.1%.
Ouwen Jin, Qinghui Xing, Zhuo Chen 0044, Ming Zhang 0018, De Ma, Ying Li 0001, Xin Du 0002, Shuibing He, Shuiguang Deng, Gang Pan 0001
IEEE Trans. Parallel Distributed Syst.3