The OAuth 2.0 protocol is a widely adopted standard for online authorization. Given its widespread use, it has received substantial attention from the research community towards assessing its security. Earlier research has primarily focused on the security of the protocol itself, or the implementation quality of popular online OAuth-based services. However, despite the numerous flaws that have been discovered in public OAuth services, there has only been limited research that directly studied the underlying OAuth middleware. In this study, we address this gap by conducting a systematic evaluation of eight popular open-source identity providers. In our analysis, we identified ten important types of security flaws among these providers. We further explore the root causes of these problems and discuss why certain parts of the OAuth standard are poorly implemented. Our findings reveal an alarming reality: we uncovered security weaknesses and vulnerabilities in seven out of eight examined middle-wares, with an average of three security issues per provider. While these weaknesses have been addressed, resulting in two CVEs, our results emphasize the importance of continued research efforts to improve the security of OAuth implementations.

The authors demonstrate that, next to allocation and scheduling of data path operations, efficient storage schemes and memory access are crucial in DSP (digital signal processor) ASIC (application-specific integrated circuit) design. For complex, medium throughput DSP applications, the authors have identified a strategy and important optimization tasks for compiling multidimensional data structures into distributed dual-port register files and single-port SRAM (static random-access memories). These techniques have been implemented in the Cathedral-II silicon compiler. The applicability of the proposed strategy has been demonstrated during the design of an 800 bit/s vocoder. Window computation reduced 23833 entries of 56 arrays to 932 locations.>

The state of the art of compiling digital signal processing (DSP) algorithms into silicon is discussed. It is indicated how digital signal processing differs from numerical data processing, including the consequences for the synthesis tools. On the basis of a broad range of DSP applications, four classes of architectures are then distinguished to serve as templates for four different synthesis systems. Although each of these four silicon compilers is tuned to a specific class of applications in order to generate area-efficient chips, they all accept as input the same behavioral DSP specification. The four selected architectural styles are best characterized by hard-wired bit-serial data-paths, microcoded multiprocessors, cooperating bit-parallel data-paths, and regular arrays. The characteristics of the first three architectures are treated in more detail in a discussion of three different Cathedral synthesis environments for their respective design. A fourth Cathedral environment, aiming at the synthesis of regular arrays, is still in an early stage of development and is not discussed. The claims for the compilers are substantiated by typical designs.>