The pervasive demand for data-intensive applications and the rapid integration of emerging technologies are driving an unprecedented transformation in wireless communication, particularly within Industry 4.0. Optimizing 5G and future networks for automated environments like smart warehouses requires advanced solutions for indoor radio propagation. To this end, this paper introduces WISVA (Wireless Infrastructure for Smart Warehouses using VAE), an AI-based framework utilizing a novel Variational Autoencoder (VAE) model (AI Contribution). The VAE's unique architecture learns complex electromagnetic (EM) wave interactions from meticulously crafted, physics-informed data tensors, enabling it to accurately model signal behavior impacted by diverse obstacles. This engineering application provides precise signal-to-interference-plus-noise ratio (SINR) heatmaps for 5G wireless bands in automated Industry 4.0 settings. We demonstrate WISVA's remarkable robustness and adaptability through its superior performance in denoising tasks, validation, and critically, extrapolation to entirely unseen warehouse layouts and configurations. Comparative analysis via reconstruction error heatmaps reveals WISVA's significantly higher accuracy against traditional autoencoders, establishing its potential as a critical enabler for efficient wireless infrastructure optimization in Industry 4.0.

The next decade is poised for a transformative shift in wireless communication technologies, driven by the increasing demand for data-intensive applications. Innovations in signal processing, network architecture estimation and design, and spectrum utilization will be critical in realizing the potential of 5G and beyond. These advancements will enable the seamless integration of emerging technologies and empower the digital transformation of industries and society. In this paper, we introduce a Variational Autoencoder (VAE) based model for indoor radio propagation modeling within an automated Industry4.0 warehouse or factory floor in the 5G wireless bands. We detail the creation of training data tensors, the architecture of our proposed VAE model, and its training using tensors that capture the impact of various interacting objects within a 5G-enabled smart warehouse infrastructure. The model is trained on multiple warehouse configurations to predict the signal-to-interference-plus-noise ratio (SINR) for both the validation dataset and unknown warehouse configurations. We present reconstruction error heatmaps to demonstrate the accuracy of our model and analyze its performance in different complex warehouse environments.

Convolutional neural networks (CNNs) have achieved significant success in various applications. Numerous hardware accelerators are introduced to accelerate CNN execution with improved energy efficiency compared to traditional software implementations. Despite the achieved success, deploying traditional hardware accelerators for bulky CNNs on current and emerging smart devices is impeded by limited resources, including memory, power, area, and computational capabilities. Recent works introduced processing-in-memory (PIM), a non-Von-Neumann architecture, which is a promising approach to tackle the problem of data movement between logic and memory blocks. However, as observed from the literature, the existing PIM architectures cannot congregate all the computational operations due to limited programmability and flexibility. Furthermore, the capabilities of the PIM are challenged by the limited available on-chip memory. To enable faster computations and address the limited on-chip memory constraints, this work introduces a novel reconfigurable approximate computing-based PIM, termed ReApprox-PIM. The proposed ReApprox-PIM is capable of addressing the two challenges mentioned above in the following manner: (i) it utilizes a programmable look-up-table (LUT)-based processing architecture that can support different approximate computing techniques via programmability, and (ii) followed by resource-efficient, fast CNN computing via the implementation of highly-optimized approximate computing techniques. This results in improved computing footprint, operational parallelism, and reduced computational latency and power consumption compared to prior PIMs relying on exact computations for CNN inference acceleration at a minimal sacrifice of accuracy. We have evaluated the proposed ReApprox-PIM on various CNN architectures, for inference applications including standard LeNet, AlexNet, ResNet-18, -34, and -50. Our experimental results show that the ReApprox-PIM achieves a speedup of 1.63× with 1.66 × lower area for the processing components compared to the existing PIM architectures. Furthermore, the proposed ReApprox-PIM achieves 2.5× higher energy efficiency and 1.3× higher throughput compared to the state-of-the-art LUT-based PIM architectures.

Processing-in-Memory (PIM) has shown great potential for a wide range of data-driven applications, especially Deep Learning and AI. However, it is a challenge to facilitate the computational sophistication of a standard processor (i.e. CPU or GPU) within the limited scope of a memory chip without contributing significant circuit overheads. To address the challenge, we propose a programmable LUT-based area-efficient PIM architecture capable of performing various low-precision floating point (FP) computations using a novel LUT-oriented operand-decomposition technique. We incorporate such compact computational units within the memory banks in a large count to achieve impressive parallel processing capabilities, up to 4x higher than state-of-the-art FP-capable PIM. Additionally, we adopt a highly-optimized low-precision FP format that maximizes computational performance at a minimal compromise of computational precision, especially for Deep Learning Applications. The overall result is a 17% higher throughput and an impressive 8-20x higher compute Bandwidth/bank compared to the state-of-the-art of in-memory acceleration.

Guest Editors Introduction: Special Issue on Network-on-Chip Architectures of the Future (NoCArc

Modern computing systems involve huge data exchange across various sections of the processing system. To facilitate this, network-on-chip (NoC) serves as a crucial infrastructure that connects the processing cores to memory, peripherals, etc. The system could be put at great risk should the NoC system become compromised. The NoCs are used in multi/many-core processors; this domain is experiencing increased threats because of hardware Trojan (HT) embedded in the multicore processing systems due to the presence of third-party entities in the system-on-chip (SoC) design pipeline. Protecting user and system level privacy becomes important in such multi core systems to enable trust. By embedding an HT in an NoC, the adversary can snoop on important insights regarding the applications executing on the system or the user profile information. An attack of such calibre can compromise privacy, thereby enabling more advanced attack on the entire system. This work demonstrates the capability of a traffic analysis attack when a few HTs are embedded in the NoC switches of a multi/many-core processor. The attack is capable of exposing sensitive information to an external malicious attacker who can then analyze the payload data with sophisticated machine learning (ML) techniques to infer the applications executing on the system. We also evaluate the performance of a generative adversarial network (GAN) strengthened attacker model that offers more robustness for data paucity scenarios. We propose a simulated annealing-based randomized routing algorithm based defense for NoCs, thus thwarting the attack. The results demonstrate that the proposed randomized routing algorithm could reduce the accuracy of identifying user profiles by the attacker from$>$98% to < 15% in multi/many-core systems.

Improving the performance of real-time Traffic Sign Recognition (TSR) applications using Deep Learning (DL) algorithms such as Convolutional Neural Networks (CNN) on software platforms is challenging due to the sheer computational complexity of these algorithms. In this work, we adopt a hardware-software combined approach to address this issue. We introduce a data-centric Processing-in-Memory (PIM) architecture that leverages Look-up-Table (LUT)-based processing for minimal data movement and superior performance and efficiency. Despite the superior performance, the limited available memory in PIM makes it complex to deploy deep CNNs. We propose merging CNN layers in this work to meet the limited resource constraints. One specific challenge in the TSR is the continuous change in the deployed environment, which makes a CNN model train over static data, leading to performance degradation over time. To address these challenges, we introduce a lightweight, performance-aware Generative Adversarial Network (GAN)-based on-device learning on PIM architecture. This compact CNN on PIM architecture attains data-level parallelism and reduces pipelining delays and makes it easier for on-device training and inference. Evaluation is performed on multiple state-of-the-art DL networks such as LeNet, AlexNet, ResNet using the German Traffic Sign Recognition Benchmark (GTSRB) Dataset, and the Belgium Traffic Sign Dataset (BTSD). With the proposed learning technique, it is observed to achieve maximum accuracy of 92.8% and 89.27% on GTSRB, and BTSD datasets. Also, it is observed the proposed mechanism maintains an average accuracy to be above 85% despite changes in the environment on all the CNNs deployed on the PIM accelerator.

Recent research has demonstrated that machine learning algorithms are vulnerable to adversarial attacks, in which small but carefully crafted input perturbations can lead to algorithm failure. It has been demonstrated that certain adversarial attack algorithms are capable of producing these types of perturbations. These attack methods are inapplicable when the attack must be generated in near real time. The use of a hardware accelerator, such as a Process-in-Memory (PIM) archi-tecture, is a potential method for addressing this issue. The PIM architecture is regarded as a superior option for data-intensive applications such as solving optimization problems and Deep Neural Networks (DNN) due to its capacity for ultra-low-latency parallel processing. However, implementing an adversarial attack algorithm directly on the PIM platform is inefficient due to the PIM architecture's complexity and overhead costs. To address this issue, we utilize a novel adversarial attack scheme based on the PIM that leverages Look-up-Table (LUT)-based processing. The proposed LUT-based PIM architecture is capable of being dynamically programmed to execute the operations necessary for an adversarial attack algorithm. Our simulations reveal that the proposed method is capable of achieving an ultra-low operating delay and energy-efficiency performance.

Processing in memory (PIM) architecture, with its ability to perform ultra-low-latency parallel processing, is regarded as a more suitable alternative to von Neumann computing architectures for implementing data-intensive applications such as Deep Neural Networks (DNN) and Convolutional Neural Networks (CNN). In this article, we present a Look-up Table (LUT) based PIM architecture aimed at CNN/DNN acceleration that replaces logic-based processing with pre-calculated results stored inside the LUTs in order to perform complex computations on the DRAM memory platform. Our LUT-based DRAM-PIM architecture offers superior performance at a significantly higher energy-efficiency compared to the more conventional bit-wise parallel PIM architectures, while at the same time avoids fabrication challenges associated with the in-memory implementation of logic circuits. Alongside, the processing elements can be programmed and re-programmed to perform virtually any operation, including operations of Convolutional, Fully Connected, Pooling, and Activating Layers of CNN/DNN. Furthermore, it is capable of operating on several combinations of bit-widths of the operand data and thereby offers a wider range of flexibility across performance, precision, and efficiency. Transmission Gate (TG) realization of the circuitry ensures minimal footprint from the PIM architecture. Our simulations demonstrate that the proposed architecture can perform AlexNet inference at a nearly 13× faster rate and 125× more efficiency compared to state-of-the-art GPU and also provides 1.35× higher throughput at 2.5× higher energy-efficiency than another recent DRAM-implemented LUT-based PIM architecture in its baseline operation mode. Moreover, it offers 12× higher frame-rate at 9× more efficiency per frame for the lowest operand precision setting, with respect to its own baseline operation mode.

Processing in Memory (PIM) is a recent novel computing paradigm that is still in its nascent stage of development. Therefore, there has been an observable lack of standardized and modular Instruction Set Architectures (ISA) for the PIM devices. In this work, we present the design of an ISA which is primarily aimed at a recent programmable Look-up Table (LUT) based PIM architecture. Our ISA performs the three major tasks of i) controlling the flow of data between the memory and the PIM units, ii) reprogramming the LUTs to perform various operations required for a particular application, and iii) executing sequential steps of operation within the PIM device. A microcoded architecture of the Controller/Sequencer unit ensures minimum circuit overhead as well as offers programmability to support any custom operation. We provide a case study of CNN inferences, large matrix multiplications, and bitwise computations on the PIM architecture equipped with our ISA and present performance evaluations based on this setup. We also compare the performances with several other PIM architectures.

Processing in Memory (PIM), a non-von Neumann computing paradigm, has emerged as a faster and more efficient alternative to the traditional computing devices for data-centric applications such as Data Encryption. In this work, we present a novel PIM architecture implemented using programmable Lookup Tables (LUT) inside a DRAM chip to facilitate massively parallel and ultra-efficient data encryption with the Advanced Encryption Standard (AES) algorithm. Its LUT-based architecture replaces logic-based computations with LUT ‘look-ups’ to minimize power consumption and operational latency. The proposed PIM architecture is organized as clusters of homogeneous, interconnected LUTs that can be dynamically programmed to execute operations required for performing AES encryption. Our simulations show that the proposed PIM architecture can offer up to 14.6× and 1.8× higher performance compared to CUDA-based implementation of AES Encryption on a high-end commodity GPU and a state-of-the-art GPU Computing Processor, respectively. At the same time, it also achieves 217× and 31.2× higher energy efficiency, respectively, than the aforementioned devices while performing AES Encryption.

Interconnection networks such as Network-on-Chips (NoCs) for multi/many-core processors are critical infrastructure of the system as they enable data communication among the processing cores, caches, memory, and other peripherals. Given the criticality of the interconnects, the system can be severely subverted if the interconnection is compromised. The threat of Hardware Trojans (HTs) penetrating complex hardware systems such as multi/many-core processors are increasing due to the increasing presence of third party players in a System-on-chip (SoC) design. Even by deploying naïve HTs, an adversary can exploit the NoC backbone of the processor and get access to communication patterns in the system. In this paper, we discuss that one or more HTs embedded in the NoC of a multi/many-core processor is capable of leaking sensitive information regarding traffic patterns to an external malicious attacker; who, in turn, can analyze the HT payload data with advanced algorithms such as machine learning to infer the applications running on the processor or reverse engineer architectural Intellectual Property (IP) of the system. Here, we entertain the idea of using routing obfuscation to achieve a desired trade-off between defense against HTs and performance penalties. We also discuss the possibility of making this trade-off a tunable design parameter that can be adjusted at run-time based on external threat perception.

Utilizing millimeter wave (mmWave) wireless communication in wireless datacenter networks, the power consumption of the networking equipment can be reduced drastically. However, security of a datacenter is one of the highest design priorities. Many studies on the security of wired datacenters including identifying the possible threats and solutions have been explored in the literature. On the contrary, being an emerging technology, no study has been conducted on the security for the wireless datacenters. Being a wireless system, it has the potential to inherit many of the threats of a typical wireless network. So, in order to successfully realize wireless datacenter architectures, it is essential to do an extensive investigation of the system from a security perspective. In this paper, we study both existing as well as novel threats and their impact on the wireless datacenter network. In addition to these conventional threats, we demonstrate the impact of a novel attack on the wireless datacenter which can be launched by leveraging its control plane.

to meet the extensive computational load presented by the rapidly growing Machine Learning (ML) and Artificial Intelligence (AI) algorithms such as Deep Neural Networks (DNNs) and Convolutional Neural Networks (CNNs). In order to obtain hardware solutions to meet the low-latency and high-throughput computational demands from these algorithms, Non-Von Neumann computing architectures such as In-memory Computing (IMC)/ Processing-in-memory (PIM) are being extensively researched and experimented with. In this survey paper, we analyze and review pioneer IMC/PIM works designed to accelerate ML algorithms such as DNNs and CNNs. We investigate different architectural aspects and dimensions of these works and provide our comparative evaluations. Furthermore, we discuss challenges and limitations in IMC research and also present feasible directions based on our observations and insight.

On-chip wireless interconnects have been demonstrated to improve the performance and energy consumption of data communication in Network-on-Chips (NoCs). However, the wireless interfaces (WIs) can be defective, rendering these broken links severely affect the performance. This makes manufacturing test of the WIs critical. While analog testing of the transceivers is possible, such methodologies are impractical in a Wireless NoC (WiNoC) due to large overheads. In addition to testing, security is another prominent challenge in WiNoCs, as the security breach can happen due to embedded hardware Trojans or through external attacker exploiting the wireless medium. The typical security measures used in general wireless networks are not practical in a WiNoC due to unique network architectures and performance requirements of such a system. However, both testing and security defense can potentially leverage a basic monitoring framework which, can detect malfunctions or anomalies. Based on this idea, we propose a unified architecture for testing and attack detection and protection of on-chip wireless interconnects. We adopt a Built-In-Self Test (BIST) methodology to enable online monitoring of the wireless interconnects which can also be reused for monitoring the security threats. We focus on manufacturing defects of the WIs for testing and persistent jamming attack for the security measures, as this kind of attack is most likely on wireless communication systems. The BIST methodology is capable of detecting faults in the wireless links with a low aliasing probability of 2.32× 10 −10 . Additionally, the proposed unified architecture is able to detect the persistent jamming with an accuracy of 99.87% and suffer < 3% communication bandwidth degradation even in the presence of attacks from either internal or external sources.

Heterogeneous multichip architectures have gained significant interest in high-performance computing clusters to cater to a wide range of applications. In particular, heterogeneous systems with multiple multicore CPUs, GPUs, and memory have become common to meet application requirements. The shared resources like interconnection network in such systems pose significant challenges due to the diverse traffic requirements of CPUs and GPUs. Especially, the performance and energy consumption of inter-chip communication have remained a major bottleneck due to limitations imposed by off-chip wired links. To overcome these challenges, we propose a wireless interconnection network to provide energy-efficient, high-performance communication in heterogeneous multi-chip systems. Interference-free communication between GPUs and memory modules is achieved through directional wireless links, while omnidirectional wireless interfaces connect cores in the CPUs with other components in the system. Besides providing low-energy, high-bandwidth inter-chip communication, the wireless interconnection scales efficiently with system size to provide high performance across multiple chips. The proposed inter-chip wireless interconnection is evaluated on two system sizes with multiple CPU and multiple GPU chips, along with main memory modules. On a system with 4 CPU and 4 GPU chips, application runtime is sped up by 3.94×, packet energy is reduced by 94.4%, and packet latency is reduced by 58.34% as compared to baseline system with wired inter-chip interconnection.

Wireless networks-on-chips (NoCs) (WiNoCs) have emerged as a possible solution to the nonscalable multihop data transmission paths in traditional wired NoC architectures. Using low-power transceivers in NoC switches, novel WiNoC architectures have been shown to achieve higher energy efficiency with improved peak bandwidth and reduced on-chip data transfer latency. However, using wireless interconnects for intrachip data transfer over an unguided medium introduces additional security vulnerabilities in on-chip communication arising from either external attackers or internal hardware Trojans. In this article, we propose a mechanism to make the wireless communication in a WiNoC secure against persistent jamming-based denial-of-service (DoS) attacks and eavesdropping (ED) from both external and internal attackers. Persistent jamming attacks on the on-chip wireless medium will cause interference in data transfer over the duration of the attack resulting in errors in contiguous bits, known as burst errors. Therefore, we use a burst-error correction code to monitor the rate of burst errors received over the wireless medium and deploy a machine-learning (ML) classifier to detect the persistent jamming attack and distinguish it from random burst errors. In the event of a persistent jamming attack, alternate routing strategies are proposed to avoid the DoS attack over the wireless medium, so that a secure data transfer can be sustained even in the presence of persistent jamming. In the event of an external ED attack, we deploy a low-latency and lightweight data scrambling method to secure communication over the wireless channel. In the case of an internal ED, we propose a mechanism to identify the attacker and prevent the attack. We evaluate the proposed techniques on a WiNoC in the presence of DoS and ED attacks from both internal and external attackers. On an average, 99.87% of the attack on DoS detection was achieved with the chosen ML classifier. A bandwidth degradation of <; 3% is experienced in the event of both DoS and ED internal attacks. The wireless interconnects are disabled in the presence of a persistent external jamming DoS attack for security, therefore eliminating the advantages of the wireless interconnections making the performance of the WiNoC comparable with that of a wired NoC. Although scrambling overheads are incurred in the presence of an external ED attack, the overheads are minimized by adopting simple XOR-based encoding and decoding.

Research in recent years has demonstrated that intra and inter-chip wireless interconnects are capable of establishing energy-efficient data communications within as well as between multiple chips. This paper presents a circuit level design of an energy-efficient millimeter wave (mm-wave) on-off keying (OOK) transmitter suitable for such wireless interconnects in 45-nm CMOS process. The transmitter consists of an NMOS cross-coupled VCO, an OOK modulator and a power amplifier. The transmitter is able to achieve maximum modulation data rate of 16Gb/s at 60GHz with the output power of -3dBm consuming a total power of 3.9mW, which translates to a bit-energy efficiency of 0.24pJ/bit.

The following topics are dealt with: network-on-chip; multiprocessing systems; network routing; system-on-chip; integrated circuit interconnections; microprocessor chips; telecommunication traffic; wireless channels; cache storage; and telecommunication network routing.

Datacenters have become the digital backbone of the modern society and consume enormous amounts of power. Significant portion of the power consumption is due to the power hungry switching fabric necessary for communication in the datacenter. Additionally, the complex cabling in traditional datacenters pose design and maintenance challenges and increase the energy cost of the cooling infrastructure by obstructing the flow of chilled air. In this work we address these problems of traditional datacenters by designing a server-to-server wireless datacenter network (DCN). We propose design methodologies for the use of 60GHz unlicensed millimeter-wave bands to establish direct communication links between servers in a DCN without the need for a conventional fabric. This will reduce the power consumption of the DCN significantly. We first demonstrate that such a power-efficient wireless DCN can sustain the traffic requirements encountered in small to mid-size real datacenters and provide data rates that are comparable to traditional DCNs. Having established the feasibility of a server-to-server wireless DCN in terms of performance, we estimate that its power consumption is lower by four to six times in comparison to a conventional DCN fabric.

Computing modules in typical data center nodes or server racks consist of several multicore chips either on a board or in a System-in-Package (SiP) environment. State-of-the-art inter-chip communication over wireline channels require data signals to travel from internal nets to the peripheral I/O ports and then get routed over the inter-chip channels to the I/O port of the destination chip. Following this, the data is finally routed from the I/O to internal nets of the destination chip over a wireline interconnect fabric. This multihop communication increases energy consumption while decreasing data bandwidth in a multichip system. Also, traditional I/O does not scale well with technology generations due to limitations of pitch. Moreover, intra-chip and inter-chip communication protocol within such a multichip system is often decoupled to facilitate design flexibility. However, a seamless interconnection between on-chip and off-chip data transfer can improve the communication efficiency significantly. Here, we propose the design of a seamless hybrid wired and wireless interconnection network for multichip systems with dimensions spanning up to tens of centimeters with on-chip wireless transceivers. We demonstrate with cycle accurate simulations that such a design increases the bandwidth and reduces the energy consumption in comparison to state-of-the-art wireline I/O based multichip communication.

Wireless interconnects have emerged as an energy-efficient interconnection paradigm for multicore chips with Networks-on-Chips (NoCs). As wireless interconnects have the unique advantage of eliminating the need to layout physical channels they provide an inherent opportunity for dynamic reconfiguration of the NoC architecture. Large temporal and spatial variability in traffic patterns is expected in large multicore chips and especially in future heterogeneous systems-on-chips integrating different kinds of cores such as CPUs, GPUs, ASICs and memory. By establishing on-demand wireless links in response to dynamically varying traffic patterns the data bandwidth and energy efficiency of NoC architectures can be improved compared to static architectures with the same raw bandwidth. We present a dynamic medium access mechanism that establishes wireless links depending on traffic requirements while reducing the overheads. Such an interconnection system incorporating wireless links in a NoC fabric will be better suited to address non-uniformity and temporal variations in traffic patterns which are expected in future large multicore chips.

With increase in complexity of multicore chips, efficiency of data transfer between cores of a chip is becoming increasingly challenging. Several novel on-chip network architectures are proposed to improve the design flexibility and communication efficiency in multicore chips. On the other hand, computing modules in typical data center nodes or server racks consist of several multicore chips on either a board or in a System-in-Package (SiP) environment. State-of-the-art interchip communication over wireline channels require data signals to travel from internal nets to the peripheral I/O ports and then get routed over the interchip channels to the destination chip. After reaching the destination chip they will be finally routed from the I/O to the internal nets there. This multihop communication increases latency and energy consumption while decreasing data bandwidth in a multichip system. Moreover, intrachip and interchip communication within such a multichip system is often decoupled to facilitate design flexibility. However, a seamless interconnection between on-chip and off-chip data transfer can improve the communication efficiency significantly. In this work we propose the design of a seamless hybrid wired and wireless interconnection network for multichip systems in a package with dimensions spanning up to tens of centimeters with on-chip wireless transceivers. This enables direct chip-to-chip communication between internal cores. We demonstrate with cycle accurate simulations that such a design increases the bandwidth and reduces the energy consumption in comparison to state-of-the-art wireline I/O based multichip communication.

On-chip wireless interconnects have emerged as a promising alternative to conventional wireline interconnects in Network-on-Chip (NoC) fabrics for multicore systems. However, it is not practical in the immediate future to arbitrarily scale up the number of wireless links without innovations in the physical layer. Here, we explore the design of a directional on-chip antenna based on a log-periodic structure. In this paper we propose the design of a wireless NoC (WiNoC) architecture with concurrent wireless links using these directional on-chip antennas. Through cycle accurate simulations we demonstrate that this novel WiNoC architecture attains better performance and energy efficiency compared to the state-of-the-art token based WiNoC of similar topology.

Multihop communication links in conventional Networks-on-Chips (NoCs) results in lower rates of data transfer and higher energy dissipation. Long-range millimeter-wave wireless interconnects were envisioned to alleviate this problem. However, the available bandwidth of the wireless channels is limited and hence an efficient media access control (MAC) scheme is required to enhance the utilization of the available bandwidth. In this article we show that with multiple simultaneous access of the shared wireless medium using a Code Division Multiple Access (CDMA) scheme the peak performance can be improved significantly while lowering energy dissipation in data transfer compared to the conventional wireline counterparts as well as state-of-the-art Wireless NoCs using similar technologies. We present a thorough analysis of the reliability in data transfer using the CDMA based wireless links and show that a reliability-aware architecture design with CDMA based wireless links can lower the energy dissipation in NoC fabrics without compromising the achievable robustness.

The millimeter-wave small-world wireless network-on-chip (mSWNoC) is an enabling interconnect architecture to design high-performance and low-power multicore chips. As the mSWNoC has an overall irregular topology, it is essential to design and optimize suitable deadlock-free routing mechanisms for it. In this paper, we quantify the latency, energy dissipation, and thermal profiles of mSWNoC architectures by incorporating irregular network routing strategies. We demonstrate that the latency, energy dissipation, and thermal profile are affected by the adopted routing methodologies. The overall system performance and thermal profile are governed by the traffic-dependent optimization of the routing methods. Our aim is to establish the energy-thermal-performance trade-offs for the mSWNoC depending on the exact routing strategy and the characteristics of the benchmarks considered.

The Network-on-Chip (NoC) paradigm is used as a scalable interconnection infrastructure for multi-core chips. To enhance the performance of conventional interconnect-based multi-core chips, on-chip wireless interconnect has emerged as a radically different technology. However, this emerging interconnect paradigm imposes significant challenges pertaining to reliable integration and design. In this paper, we focus on two types of mm-wave wireless NoC architectures. One is a hierarchical architecture with long-range wireless shortcuts and the other is a power-law connectivity based small-world network without any hierarchy. We demonstrate that though the hierarchical architecture offers more bandwidth with lower energy dissipation than the small-world-based counterpart, it has significantly more area overhead. Also, the power-law connectivity based small-world wireless NoC is more robust in presence of wireless link failures.

Traditional multi-core designs, based on the Network-on-Chip (NoC) paradigm, suffer from high latency and power dissipation as the system size scales up due to the inherent multi-hop nature of communication. Introducing long-range, low power, and high-bandwidth, single-hop links between far apart cores can significantly enhance the performance of NoC fabrics. In this paper, we propose design of a small-world network based NoC architecture with on-chip millimeter (mm)-wave wireless links. The millimeter wave small-world NoC (mSWNoC) is capable of improving the overall latency and energy dissipation characteristics compared to the conventional mesh-based counterpart. The mSWNoC helps in improving the energy dissipation, and hence the thermal profile, even further in presence of network-level dynamic voltage and frequency scaling (DVFS) without incurring any additional latency penalty.

The Network-on-Chip (NoC) paradigm has emerged as a scalable interconnection infrastructure for modern multicore chips. However, with growing levels of integration, the traditional NoCs suffer from high latency and energy dissipation in on-chip data transfer due to conventional multihop metal/dielectric-based interconnects. Three-dimensional integration, on-chip photonics, RF, and wireless links have been proposed as radical low-power and low-latency alternatives to the conventional planar wire-based designs. Wireless NoCs with Carbon NanoTube (CNT) antennas are shown to outperform traditional wire-based NoCs significantly in achievable data rate and energy dissipation. However, such emerging and transformative technologies will be prone to high levels of failures due to various issues related to manufacturing challenges and integration. On the other hand, several naturally occurring complex networks such as colonies of microbes and the World Wide Web are known to be inherently robust against high rates of failures and harsh environments. This article advocates adoption of such complex network-based architectures to minimize the effect of wireless link failures on the performance of the NoC. Through cycle-accurate simulations it is shown that the wireless NoC architectures inspired by natural complex networks perform better than their conventional wired counterparts even in the presence of high degrees of link failures. We demonstrate the robustness of the proposed wireless NoC architecture by incorporating both uniform and application-specific traffic patterns.

The Network-on-chip (NoC) is an enabling technology to integrate large numbers of embedded cores on a single die. The existing methods of implementing a NoC with planar metal interconnects are deficient due to high latency and significant power consumption arising out of multihop links used in data exchange. To address these problems, we propose design of a hierarchical small-world wireless NoC architecture where the multihop wire interconnects are replaced with high-bandwidth and single-hop long-range wireless shortcuts operating in the millimeter (mm)-wave frequency range. The proposed mm-wave wireless NoC (mWNoC) outperforms the corresponding conventional wireline counterpart in terms of achievable bandwidth and is significantly more energy efficient. The performance improvement is achieved through efficient data routing and optimum placement of wireless hubs. Multiple wireless shortcuts operating simultaneously further enhance the performance, and provide an energy-efficient solution for design of communication infrastructures for multicore chips.

Traditional many-core designs based on the Network-on-Chip (NoC) paradigm suffer from high latency and power dissipation as the system size scales up due to their inherent multi-hop communication. NoC performance can be significantly enhanced by introducing long-range, low power, and high-bandwidth single-hop wireless links between far apart cores. This paper presents a design methodology and performance evaluation for a hierarchical small-world NoC with CMOS compatible on-chip millimeter (mm)-wave wireless long-range communication links. The proposed wireless NoC offers significantly higher bandwidth and lower energy dissipation compared to its conventional non-hierarchical wired counterpart in presence of both uniform and non-uniform traffic patterns. The performance improvement is achieved through efficient data routing and optimum placement of wireless hubs. Multiple wireless shortcuts operating simultaneously provide an energy efficient solution for design of many-core communication infrastructures.

Wireless Network-on-Chip (NoC) architectures have emerged as an enabling solution to design scalable NoC fabrics for massive many-core chips. However, such massive levels of integration of Intellectual Property (IP) cores make the chips vulnerable to malicious intrusions from untrustworthy processes or vendors. Hence, resilience to various types of hardware security threats is imperative in future many-core chips. In this paper we develop a design methodology to increase the resilience of a wireless NoC to Denial-of-Service (DoS) attacks. We demonstrate that the proposed architecture can sustain higher data transfer rates at lower energy dissipation with the spread of DoS attacks compared to conventional mesh based NoCs.

Multi-hop data transfer in conventional Networks-on-Chips (NoCs) results in lower rates of data transfer and higher energy dissipation. Long-range millimeter-wave wireless interconnects were envisioned to alleviate this problem. However, as the bandwidth of the wireless channels is limited an efficient media access control (MAC) scheme is required to enhance the utilization of the available bandwidth. In this paper we show that with multiple simultaneous access of the shared wireless medium using a traffic-adaptive Code Division Multiple Access (CDMA) scheme the peak performance can be improved significantly while lowering energy dissipation in data transfer compared to the conventional wireline counterparts.

Massive levels of integration are making modern multicore chips all pervasive in several domains. High performance, robustness, and energy-efficiency are crucial for the widespread adoption of such platforms. Networks-on-Chip (NoCs) have emerged as communication backbones to enable a high degree of integration in multicore Systems-on-Chip (SoCs). Despite their advantages, an important performance limitation in traditional NoCs arises from planar metal interconnect-based multihop links with high latency and power consumption. This limitation can be addressed by drawing inspiration from the evolution of natural complex networks, which offer great performance-cost trade-offs. Analogous with many natural complex systems, future multicore chips are expected to be hierarchical and heterogeneous in nature as well. In this article we undertake a detailed performance evaluation for hierarchical small-world NoC architectures where the long-range communications links are established through the millimeter-wave wireless communication channels. Through architecture-space exploration in conjunction with novel power-efficient on-chip wireless link design, we demonstrate that it is possible to improve performance of conventional NoC architectures significantly without incurring high area overhead.

introduction Share on Introduction to the special issue on sustainable and green computing systems Editors: Partha Pratim Pande Washington State University Washington State UniversityView Profile , Amlan Ganguly Rochester Institute of Technology Rochester Institute of TechnologyView Profile Authors Info & Claims ACM Journal on Emerging Technologies in Computing SystemsVolume 8Issue 4Article No.: 26pp 1–3https://doi.org/10.1145/2367736.2367737Published:30 November 2012Publication History 1citation496DownloadsMetricsTotal Citations1Total Downloads496Last 12 Months10Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

While traditional cluster computers are more constrained by power and cooling costs for solving extreme-scale (or exascale) problems, the continuing progress and integration levels in silicon technologies make possible complete end-user systems on a single chip. This massive level of integration makes modern multicore chips all pervasive in domains ranging from climate forecasting and astronomical data analysis, to consumer electronics, smart phones, and biological applications. Consequently, designing multicore chips for exascale computing while using the embedded systems design principles looks like a promising alternative to traditional cluster-based solutions. This paper aims to present an overview of new, far-reaching design methodologies and run-time optimization techniques that can help breaking the energy efficiency wall in massively integrated single-chip computing platforms.

The soaring power dissipation of computing infrastructures has effectively become a key performance bottleneck. At the same time, thermal issues arising from power hungry devices result in compromising reliability of such systems. At present, the processor cores within a chip multiprocessor (CMP) are interconnected using on-chip networks. At the same time, the emerging era of cloud computing and the associated large-scale distributed computing model are stretching the limits of computer networking. Hence, as an essential and pervasive fabric that binds all computing machinery, there is an underlying network that appears with varying scale and characteristics. In this paper, we take a look at methodologies for better management of the power budget across the cross-section of computing systems traversing the boundary between micro-level on-chip networks to macro-level cloud computing. We discuss methodologies for power and thermal management both at micro and macro scales and explore the role of one in reducing the power budget of the other.

The Network-on-Chip (NoC) paradigm has emerged as a scalable interconnection infrastructure for modern multi-core chips. However, with growing levels of integration, the traditional NoCs suffer from high latency and energy dissipation in on-chip data transfer due to conventional metal/dielectric based interconnects. Three-dimensional integration, on-chip photonic, RF and wireless links have been proposed as radical low-power and low-latency alternatives to the conventional planar wire-based designs. Wireless NoCs with Carbon Nanotube (CNT) antennas are shown to outperform traditional wire based NoCs by several orders of magnitude in power dissipation and latency. However such transformative technologies will be prone to high levels of faults and failures due to various issues related to manufacturing and integration. On the other hand, several naturally occurring complex networks such as colonies of microbes and the internet are known to be inherently fault-tolerant against high rates of failures and harsh environments. This paper proposes to adopt such complex network based architectures to minimize the effect of wireless link failures on the performance of the NoC. Through cycle accurate simulations it is shown that the wireless NoC architectures inspired by natural complex networks perform better than their conventional wired counterparts even in the presence of a high degree of faults.

Multicore platforms are emerging trends in the design of System-on-Chips (SoCs). Interconnect fabrics for these multicore SoCs play a crucial role in achieving the target performance. The Network-on-Chip (NoC) paradigm has been proposed as a promising solution for designing the interconnect fabric of multicore SoCs. But the performance requirements of NoC infrastructures in future technology nodes cannot be met by relying only on material innovation with traditional scaling. The continuing demand for low-power and high-speed interconnects with technology scaling necessitates looking beyond the conventional planar metal/dielectric-based interconnect infrastructures. Among different possible alternatives, the on-chip wireless communication network is envisioned as a revolutionary methodology, capable of bringing significant performance gains for multicore SoCs. Wireless NoCs (WiNoCs) can be designed by using miniaturized on-chip antennas as an enabling technology. In this paper, we present design methodologies and technology requirements for scalable WiNoC architectures and evaluate their performance. It is demonstrated that WiNoCs outperform their wired counterparts in terms of network throughput and latency, and that energy dissipation improves by orders of magnitude. The performance of the proposed WiNoC is evaluated in presence of various traffic patterns and also compared with other emerging alternative NoCs.

In a traditional Network-on-Chip (NoC), latency and power dissipation increase with system size due to its inherent multi-hop communications. The performance of NoC communication fabrics can be significantly enhanced by introducing long-range, low power, high bandwidth direct links between far apart cores. In this paper a design methodology for a scalable hierarchical NoC with on-chip millimeter (mm)-wave wireless links is proposed. The proposed wireless NoC offers significantly higher throughput and lower energy dissipation compared to its conventional multi-hop wired counterpart. It is also demonstrated that the proposed hierarchical NoC with long range wireless links shows significant performance gains in presence of various application-specific traffic and multicast scenarios.

Network-on-chip (NOC) is emerging as a revolutionary methodology to integrate numerous intellectual property blocks in a single die. It is the packet switching-based communications backbone that interconnects the components on multicore system-on-chip (SoC). A major challenge that NOC design is expected to face is related to the intrinsic unreliability of the interconnect infrastructure under technology limitations. By incorporating error control coding schemes along the interconnects, NOC architectures are able to provide correct functionality in the presence of different sources of transient noise and yet have lower overall energy dissipation. In this paper, designs of novel joint crosstalk avoidance and triple-error-correction/quadruple-error-detection codes are proposed, and their performance is evaluated in different NOC fabrics. It is demonstrated that the proposed codes outperform other existing coding schemes in making NOC fabrics reliable and energy efficient, with lower latency.

With the well-known trend of CMOS scaling as per Moore’s Law, traditional on-chip interconnect systems are reaching the point of having a very limited ability to meet the performance needs and specifications of Systems-on-Chip (SoCs). The conventional two-dimensional (2D) copper-based IC has inherent limitations due to the geometrical constraints of the planar structure. Innovative interconnect paradigms based on optical technologies, RF/wireless, carbon nanotubes, or 3D integration are promising alternatives that may indeed overcome the challenges encountered. In this paper we present an overview of different emerging non-traditional approaches to achieve massive degree of integration in a single chip. The advantages and underlying challenges of each method are highlighted.

Three dimensional (3D) network on chip (NoC) has attracted researchers' attention recently. 3D NoCs are capable of achieving better system throughput and lower latency compared to the corresponding 2D implementations. To fully exploit the performance benefits of 3D architectures, it is imperative to address signal integrity issues in the design phase and its implications on energy dissipation. In this work we show that by incorporating joint crosstalk avoidance and multiple error correction schemes it is possible to enhance the robustness and reduce the energy dissipation simultaneously for both the 3D and more conventional planar NoC architectures. The achievable energy savings in 3D NoCs is significantly more than that in 2D structures.

Commercial designs are currently integrating from 10 to 100 embedded functional and storage blocks in a single SoC and the number is likely to increase significantly in the near future. With this ever increasing degree of integration, design of communication architectures for big SoCs is a challenge. The communication requirements of these large multi processor SoCs (MP-SoCs) are convened by the emerging network-on-a-chip (NoC) paradigm. The basic operations of NoC infrastructures are governed by on-chip packet-switched networks. Crosstalk between adjacent wires is an issue in NoC communication fabrics and it can cause timing violations and extra power dissipation. Crosstalk avoidance codes (CACs) can be used to improve signal integrity and also reduce the coupling capacitance and hence the energy dissipation of a wire segment. By incorporating crosstalk avoidance coding (CAC) in NoC data streams we are able to reduce communication energy, which will help to decrease the energy dissipation as a whole