The exponential growth of the Internet of Things (IoT) in the 5G era has significantly heightened the demand for secure communication among numerous edge devices. While lattice-based cryptography has gained prominence as a quantum-resistant alternative to traditional public-key cryptosystems vulnerable to quantum attacks, its high computational complexity remains a critical barrier for resource-constrained IoT edge devices. In this paper, we propose a configurable and efficient public-key cryptographic circuit architecture that achieves an optimal area-performance balance through three key innovations. First, we introduce a parameter-adaptive coefficient generation unit that compresses hash round constants, thereby reducing circuit redundancy and memory overhead. Second, we present a four-channel even-odd parallel butterfly operation architecture, with collaborative optimization of the butterfly unit (BFU) and data storage scheme. Finally, we optimize data flow scheduling between functional modules under resource constraints, significantly enhancing circuit compactness and bandwidth utilization. FPGA prototyping on the Xilinx Artix-7 platform demonstrates that the Kyber-1024 process is completed in just 11.75k clock cycles, while the hardware efficiency improvements range from 1.2× to 7.3× over existing state-of-the-art designs, maintaining an excellent area-performance trade-off. ASIC implementation using SMIC 40nm CMOS technology achieves a 332MHz operating frequency, with hardware efficiency improvements ranging from 6.3× to 57× compared to recent implementations. Therefore, this work establishes a new paradigm for deploying post-quantum cryptography in latency-sensitive IoT applications.

The Paillier scheme, widely recognized as the most prevalent additive homomorphic encryption paradigm, faces significant challenges in Internet of Things (IoT) applications due to latency, power, and hardware overhead. This paper proposes an efficient Paillier homomorphic encryption circuit for IoT, integrating Chinese Remainder Theorem (CRT) acceleration. First, we propose an algorithm framework tailored for hardware reuse that supports multiple functionalities of the Paillier scheme. It introduces an Montgomery modular multiplication (MMM) algorithm with superior Area-Time Product (ATP) to implement core computations, and reduces hardware cost by reusing MMM to replace other computational units. Then, a computational unit reuse architecture based on the algorithmic framework is designed to reduce resource overhead. Moreover, a split-coupled MMM circuit design is proposed to counteract computational resource expansion induced by CRT operations. The hardware design is synthesized under SMIC 40 nm CMOS technology. The evaluation shows that the proposed scheme provides a high-performance Paillier circuit design with less area and lower power, offering an effective solution for data security processing in IoT.

Chaotic encryption is applied as a lightweight symmetric cryptography in Internet of Things (IoT). In symmetric encryption, system security depends on the randomness of the encryption sequence. However, the chaotic algorithm cannot be efficiently implemented with high precision in IoT resource-constrained circumstance. The cyclic effect of the algorithm under limited precision makes the sequence randomness not enough, while the exponential enhance in overhead by increasing the precision is not satisfy the lightweight goal. Therefore, a reconfigurable chaotic encryption ASIC with dynamic precision is proposed. Initially, a reconfigurable chaotic combination strategy based on multidimensional perturbations is proposed to improve sequence randomness. Second, a reconfigurable architecture with resource sharing and specified computation units are designed to effectively reduce the overhead of the algorithm hardware implementation. In addition, dynamic precision architecture is employed to provide tradeoff between precision and power consumption. Finally, the security results demonstrate that the scheme achieves satisfactory various metrics. The synthesis results by using 65-nm CMOS technology shows that its area is only 11.8k$\mu {\mathrm { m}}^{2}$, with 179.6-$\mu $W power and 11.2-pJ/bit energy efficiency at 50 MHz, which achieves lower overhead compared to the existing hybrid chaotic encryption designs.

With the rapid development of the Internet of Things (IoT), device and data security has attracted huge academic attention in recent years since conventional security methods are barely feasible in IoT circumstances. Traditional encryption methods require extensive computation complexity, which requires several hardware resources and power consumption. Meanwhile, due to the low-power requirement, most IoT devices are lightweight with limited computing and storage capabilities. The dilemma leads to the need for a lightweight encryption method with decent data protection strength. Chaotic encryption can be applied in the IoT because of the characteristics of determinacy and strong randomness. However, its safety and hardware overhead are positively correlated with implementation precision. Therefore, this article performs a quantitative analysis of the system under different precision conditions. Then, a hybrid chaotic encryption scheme with dynamic precision is proposed, which balances power consumption and security protection level. Finally, the proposed design is implemented by Verilog and synthesized using SMIC 65-nm CMOS technology. The evaluation results proved that the proposed ASIC provides decent encryption strength under diverse precision, effectively overcoming the influence of limited precision with low-hardware resources and power consumption.