General-Purpose GPUs (GPGPUs) are ideal for parallel processing and high throughput. However, efficient on-chip memory use is challenging due to resource conflicts between threads. This leads to sub-optimal throughput, highlighting the need for better memory designs. As compute demand grows, GPUs with more Streaming Multiprocessors (SMs) emerge, increasing bandwidth needs and intensifying Network-on-Chip (NoC) traffic. Current GPUs partition the shared Last-Level Cache (LLC) into uniform slices shared by all SMs. While this reduces miss rates, workloads with high inter-SM data sharing benefit more from private LLCs, which reduce contention and improve bandwidth. We propose a dynamic profiling method to evaluate data sharing across SMs during execution. Using this, we present a logistic regression-based decision mechanism to switch between shared and private LLC configurations at runtime, with a twenty five thousand cycle reconfiguration epoch (compared to 1 million cycles in the state-of-the-art). Our approach boosts performance by up to 56% over the baseline and 29% over state-of-the-art methods. It also reduces stalls by 71% over the baseline and 59% over state-of-the-art approach.

Modern processors use caches to reduce memory access time. However, their limited size leads to frequent misses, requiring an efficient replacement policy. The Least Recently Used (LRU) policy is widely adopted for its effectiveness but becomes impractical in highly associative caches due to its high area and power costs. To address inefficiencies in the last-level cache (LLC), researchers have proposed sophisticated replacement policies. However, their complexity and hardware overhead make them unsuitable for level-one (L1) and leveltwo (L2) caches, which require fast and lightweight decisionmaking. Additionally, low-cost microcontrollers demand simple and efficient replacement mechanisms. This paper introduces the Lightweight Cache Replacement Policy (LiC) as a low-cost, power-efficient alternative to LRU. Unlike conventional policies that focus on eviction decisions, LiC prioritizes protecting the last accessed block. This approach significantly reduces hardware complexity and power consumption while maintaining performance. We evaluate LiC through simulations in both single-core and multi-core environments. Results show that LiC matches LRU’s performance while drastically reducing storage overhead. Compared to sophisticated LLC replacement policies, it reduces storage costs by up to $28 \times$. Against low-cost policies like NRU and PLRU, it achieves $4 \times$ and $3.75 \times$ lower storage demands. Additionally, LiC reduces area overhead by $16 \times$ compared to LRU. With its low hardware overhead and strong performance, LiC emerges as an efficient and scalable solution across all cache levels.

Micro-architectural attacks exploit intrinsic vulnerabilities within computing systems, circumventing advanced security techniques such as cryptographic algorithms, access control policies, and secure enclaves. These attacks encompass a range of methodologies, including cache timing side-channel attacks like Flush+Reload, Flush+Flush, and Prime+Probe, as well as speculative execution attacks such as Spectre and Meltdown. These exploits leverage specific characteristics of micro-architecture to infer sensitive data, posing a significant threat to system security. Cache timing side-channel attacks exploit the inclusive nature of the last-level cache (LLC) to deduce the memory access patterns of victim processes. By observing the timing variations associated with cache hits and misses, attackers can extract confidential information, such as cryptographic keys. Although existing mitigation strategies provide a level of security, they typically do so at the expense of system performance and increased hardware. These trade-offs limit the practical applicability of such defences in performance-critical environments. This paper proposes S-Clflush: Secure Clflush, an innovative defence mechanism specifically designed to counter flush-based cache timing side-channel attacks. S-Clflush achieves this by modifying the existing clflush instruction to prevent attackers from inferring memory access patterns based on cache access latency. Unlike traditional mitigation techniques, S-Clflush enhances security without incurring performance degradation or additional area overhead. The proposed mechanism is formally verified to ensure its security guarantees. Our evaluation against the state-of-the-art mitigation technique TimeCache shows a 0.5% improvement in performance and a 58% reduction in MPKI on average without adding area overhead.

Graph analytics is powering a wide variety of applications in the domains of cybersecurity, contact tracing, and social networking. It consists of various algorithms (or workloads) that investigate the relationships between entities involved in transactions, interactions, and organizations. CPU-based graph analytics is inefficient because their cache hierarchy performs poorly owing to highly irregular memory access patterns of graph workloads. Policies managing the cache hierarchy in such systems are ignorant to the locality demands of different data types within graph workloads, and therefore are suboptimal. In this paper, we conduct an in-depth data type aware characterization of graph workloads to better understand the cache utilization of various graph data types. We find that different levels of the cache hierarchy are more sensitive to the locality demands of certain graph data types than others. Hence, we propose GRACE, a graph data-aware cache management technique, to increase cache hierarchy utilization, thereby minimizing off-chip memory traffic and enhancing performance. Our thorough evaluations show that GRACE, when augmented with a vertex reordering algorithm, outperforms a recent cache management scheme by up to 1.4×, with up to 27% reduction in expensive off-chip memory accesses. Thus, our work demonstrates that awareness of different graph data types is critical for effective cache management in graph analytics.