This paper describes a fully synthesizable digital-to-analog converter (DAC). It is important to develop an automated netlist generation and synthesizable design methodology for mixed-signal circuits. To fill in the scarcity of synthesizable DACs, we propose a multi-bit full-synthesizable current DAC using shifting current mirror architecture with a multi-segmented data weighted averaging (MSeDWA) mismatch correction algorithm. It provides robustness against process, voltage, and temperature (PVT) variations by means of a programmable bias generator, which suppresses the circuit variations by >2.7 ×. The use of power-gating standard cells provides a flexible selection of current mirror types, thus achieving a widening of the voltage operation range. Moreover, stage separation and appropriate gain configuration ensure high linearity.With the MSeDWA technique, the total harmonic distortion (THD) is further improved by 7.7 dB. Operating between 14 MHz to 56 MHz, the analog and digital circuits consume 8.64-56.64 μW and 217-629 μW, respectively. The proposed circuit has demonstrated an excellent energy efficiency of 0.03 μW/kHz while maintaining a maximum THD of 39.9 dB (1.01%).

This paper presents a VCO-based ADC design for use in flexible electronics, specifically leveraging Low-Temperature Polysilicon Thin-Film Transistor (LTPS TFT) technology. The design achieves a resolution of 8.11 bits at a 20 MHz sampling rate with a bandwidth (BW) of 2.5kHz. A linearity compensation technique combining a resistive input stage with a frequency-dependent resistor (FDR)-based feedback loop significantly enhances the VCO linearity. Simulation results validate the design, exhibiting an R2value of 0.9999 for the VCO tuning curve, a Signal-to-Noise and Distortion Ratio (SNDR) of 50.57 dB, and a Spurious-Free Dynamic Range (SFDR) of 52.34 dB at a supply voltage of 10V. The proposed design also features the lowest Figure of Merit (FoM) (0.73 nJ/conversion-step) compared with the state-of-the-art.