VLDB 2026 Research / reviewers in the wild / expert
Alireza Sanaee
dblp:295/8830
· DBLP profile ↗
7ranked-venue papers
2as first author
7since 2021 · last 2026
0000-0001-6461-1650ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 1 first-author · 3 since 2021Computer networks · 3 · 1 first-author · 3 since 2021Software engineering, systems software and programming languages · 3 · 1 first-author · 3 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Enabling Fast Networking in the Public CloudabstractDespite a decade of research, most high-performance userspace network stacks remain impractical for public cloud tenants developing their applications atop Virtual Machines (VMs). We identify two root causes: (1) reliance on specialized NIC features (e.g., flow steering, deep buffers) absent in commodity cloud vNICs, and (2) rigid execution models ill-suited to diverse application needs. We present Machnet, a highperformance and flexible userspace network stack designed for public cloud VMs. Machnet uses only a minimal set of vNIC features that any major cloud provider supports. It also relies on a microkernel architecture to enable flexible application execution. We evaluate Machnet across three major public clouds and on production-grade applications, including a key-value store, an HTTP server, and a statemachine replication system. We release Machnet at https: //github.com/microsoft/machnet. Alireza Sanaee, Vahab Jabrayilov, Ilias Marinos, Farbod Shahinfar, Divyanshu Saxena, Gianni Antichi, Kostis Kaffes |
ASPLOS (2) | 1 |
| 2024 | Scalable and Effective Page-table and TLB management on NUMA Systems
Qingxuan Kang, Hao-Wei Tee, Kyle Timothy Ng Chu, Alireza Sanaee, Djordje Jevdjic |
USENIX ATC | 5 |
| 2024 | Morpheus: A Run Time Compiler and Optimizer for Software Data PlanesabstractState-of-the-art approaches to design, develop and optimize software packet-processing programs are based on static compilation: the compiler’s input is a description of the forwarding plane semantics and the output is a binary that can accommodate any control plane configuration or input traffic. In this paper, we demonstrate that tracking control plane actions and packet-level traffic dynamics at run time opens up new opportunities for code specialization. We present Morpheus, a system working alongside static compilers that continuously optimizes the targeted networking code. We introduce a number of new techniques, from static code analysis to adaptive code instrumentation, and we implement a toolbox of domain specific optimizations that are not restricted to a specific data plane framework or programming language. We apply Morpheus to several systems, from eBPF and DPDK programs including Katran, Meta’s production-grade load balancer to container orchestration solutions such a Kubernets. We compare Morpheus to state-of-the-art optimization frameworks and show that it can bring up to 2x throughput improvement, while halving the 99th percentile latency. Sebastiano Miano, Alireza Sanaee, Fulvio Risso, Gábor Rétvári, Gianni Antichi |
IEEE/ACM Trans. Netw. | 2 |
| 2022 | Domain specific run time optimization for software data planesabstractState-of-the-art approaches to design, develop and optimize software packet-processing programs are based on static compilation: the compiler's input is a description of the forwarding plane semantics and the output is a binary that can accommodate any control plane configuration or input traffic. Sebastiano Miano, Alireza Sanaee, Fulvio Risso, Gábor Rétvári, Gianni Antichi |
ASPLOS | 2 |
| 2022 | OS-level Implications of Using DRAM Caches in Memory DisaggregationabstractMemory disaggregation has attracted great attention recently due to its benefits in resource utilization efficiency, isolation of failures, and easier reconfiguration of memory hardware. However, applications running on a system with disaggregated memory are expected to suffer from performance degradation due to increased remote memory access latency and network contention. The performance gap is meant to be bridged using DRAM caches on the processor side, which would filter out most of the network traffic.This work examines the overheads of the disaggregated memory abstraction. By experimenting with both micro-benchmarks and production applications, we observe severe degradation in memory access latency and potential bottlenecks within the OS kernel. These bottlenecks could potentially be avoided through low-level optimizations in memory management tailored for memory disaggregation. Hao-Wei Tee, Alireza Sanaee, Soh Boon Jun, Djordje Jevdjic |
ISPASS | 3 |
| 2022 | Backdraft: a Lossless Virtual Switch that Prevents the Slow Receiver Problem
Alireza Sanaee, Farbod Shahinfar, Gianni Antichi, Brent E. Stephens |
NSDI | 1 |
| 2021 | The case for network functions decompositionabstractThis paper makes a case for writing unrestricted eBPF network functions which then get automatically decomposed between kernel and user-space. Farbod Shahinfar, Sebastiano Miano, Alireza Sanaee, Giuseppe Siracusano, Roberto Bifulco, Gianni Antichi |
CoNEXT | 3 |