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Paul Reckamp

dblp:296/0612 · DBLP profile ↗
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1ranked-venue papers
0as first author
1since 2021 · last 2023
0009-0005-0460-5378ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Reconfigurable computing and FPGAs · 56% Embedded and real-time systems · 44%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Reconfigurable computing and FPGAs › FPGA high-level synthesis
FPGA scheduling
0.712023
Nimblock: Scheduling for Fine-grained FPGA Sharing through Virtualization · ISCA 2023
Reconfigurable computing and FPGAs
FPGA virtualization
0.712023
Nimblock: Scheduling for Fine-grained FPGA Sharing through Virtualization · ISCA 2023
Embedded and real-time systems › real-time scheduling
preemptive scheduling
0.712023
Nimblock: Scheduling for Fine-grained FPGA Sharing through Virtualization · ISCA 2023
Embedded and real-time systems › real-time scheduling
deadline-aware scheduling
0.212023
Nimblock: Scheduling for Fine-grained FPGA Sharing through Virtualization · ISCA 2023
Embedded and real-time systems
real-time scheduling
0.212023
Nimblock: Scheduling for Fine-grained FPGA Sharing through Virtualization · ISCA 2023

Methods — techniques the papers use, named apart from their topics

time-multiplexing · 0.7space-multiplexing · 0.7overlay architecture · 0.7
YearPublicationVenuePosition
2023 Nimblock: Scheduling for Fine-grained FPGA Sharing through Virtualization
abstract
As FPGAs become ubiquitous compute platforms, existing research has focused on enabling virtualization features to facilitate finegrained FPGA sharing. We employ an overlay architecture which enables arbitrary, independent user logic to share portions of a single FPGA by dividing the FPGA into independently reconfigurable slots. We then explore scheduling possibilities to effectively time- and space-multiplex the virtualized FPGA by introducing Nimblock. The Nimblock scheduling algorithm balances application priorities and performance degradation to improve response time and reduce deadline violations. Unlike other algorithms, Nimblock explores preemption as a scheduling parameter to dynamically change resource allocations, and automatically allocates resources to enable suitable parallelism for an application without additional user input. In our exploration, we evaluate five scheduling algorithms: a baseline, three existing algorithms, and our novel Nimblock algorithm. We demonstrate system feasibility by realizing the complete system on a Xilinx ZCU106 FPGA and evaluating on a set of real-world benchmarks. In our results, we achieve up to 5.7× lower average response times when compared to a no-sharing and no-virtualization scheduling algorithm and up to 2.1× average response time improvement over competitive scheduling algorithms that support sharing within our virtualization environment. We additionally demonstrate up to 49% fewer deadline violations and up to 2.6× lower tail response times when compared to other high-performance algorithms.
Meghna Mandava, Paul Reckamp, Deming Chen
ISCA2