The development of Ferroelectric Field-Effect Transistor (FeFET) manufacturing requires high-quality test solutions, yet research on FeFET testing is still in a nascent stage. To generate a dedicated test method for FeFETs, it is critical to have a deep understanding of manufacturing defects and accurately model them. In this work, we introduce the unique defect, Anomalous Charge Trapping (ACT), in FeFETs. The ACT-defective FeFET is characterized, and the physical mechanism of the defect is explained. Then, we apply the Deviceaware Test (DAT) method to design a specific ACT-defective FeFET model, which includes the physical impact of the defect on the electrical parameters of defect-free models, and calibrate the model with measurement data. Fault modeling is performed based on circuit-level simulations, and dedicated test solutions are proposed.

Convolutional Neural Networks (CNNs) are widely employed in various domains, including safety-critical applications such as autonomous driving. In these scenarios, the reliability of CNNs can be compromised by hardware faults occurring during inference, potentially leading to severe consequences. Evaluating the resilience of CNNs to hardware faults is primarily conducted through Fault Injection (FI) campaigns. However, a significant challenge lies in selecting an appropriate workload. Typically, the entire test set is applied for every injected fault, making the process highly time-consuming and posing difficulties for timely assessments. This paper investigates image selection strategies to rank inputs from the test dataset based on their difficulty in being classified by the CNN. The objective is to identify a minimal subset of test data that enables reliable CNN assessment while reducing computational overhead. By prioritizing challenging samples, the proposed method focuses on inputs that are more likely to reveal network vulnerabilities under fault conditions, enhancing the efficiency of the reliability evaluation process. Experimental results demonstrate that using such a subset of the test data suffices to estimate the number of critical faults for at least one image. This approach not only accelerates the reliability evaluation but also provides novel insights into CNN reliability, offering a practical framework for continuous assessments.

Microcontroller (MCU) performance screening ensures that devices meet critical specifications, such as maximum operating frequency ($F_{\max }$). On-chip Speed Monitors (SMONs), implemented as ring oscillators, provide process-correlated signals that can be used to estimate $F_{\text {max }}$ via machine learning (ML). However, traditional ML models require substantial domain expertise, extensive feature engineering, hyperparameter tuning, and dataset-specific training, limiting their scalability and generalization. In this preliminary study, we explore the use of TabPFN, a pretrained Tabular Foundation Model (TabFM) based on In-Context Learning (ICL), for MCU performance prediction. TabPFN eliminates the need for task-specific training or tuning by conditioning directly on labeled examples provided at inference time, enabling few-shot and zero-shot learning. We evaluate TabPFN on two distinct MCU datasets and compare its performance with conventional ML models, including tree-based and linear approaches. Our results show that TabPFN consistently achieves competitive accuracy with minimal human supervision, demonstrating its potential as a fast, generalizable, and low-maintenance alternative for performance screening in semiconductor manufacturing.

Microcontroller (MCU) performance screening ensures devices meet the maximum operating frequency Fmaxspecification. Speed Monitors (SMONs), implemented as ring oscillators, are used to estimate Fmax. Traditional machine learning (ML) models have been explored for this task but require extensive feature engineering and tuning. This work investigates Tabular Foundation Models, specifically TabPFN, for MCU performance prediction. TabPFN leverages in-context learning, enabling accurate inference without dataset-specific training. We evaluate its performance on a composite dataset combining four distinct MCU product families. Results show that TabPFN matches or exceeds baseline ML models while eliminating the need for manual optimization, offering a promising direction for efficient screening in semiconductor manufacturing with minimal human supervision

Ferroelectric Field-Effect Transistors (FeFETs) are promising candidates for non-volatile memory (NVM) technologies, especially in embedded systems and edge computing. However, due to their physical characteristics, FeFETs exhibit unique defects—such as Threshold Voltage Shifting (TVS) caused by trap charges in the oxide layer—that are not captured by conventional defect models. This study adopts the Device-Aware Test (DAT) methodology to model these defects by incorporating their impact into the electrical parameters, calibrated using measurement data. Defect injection, circuit-level simulations, and fault analysis are performed to derive realistic fault models. Finally, the March algorithm and Design-for-Test (DfT) techniques are proposed to effectively detect these defects.

In safety-critical applications, microcontrollers must meet stringent quality and performance standards, including the maximum operating frequency$F_{\max}$. Machine learning models have proven effective in estimating$F_{\max}$by utilizing data from on-chip ring oscillators. Previous research has shown that increasing the number of ring oscillators on board can enable the deployment of simple linear regression models to predict$F_{\max}$. However, the scarcity of labeled data that characterize this context poses a challenge in managing high-dimensional feature spaces; moreover, a very high number of ring oscillators is not desirable due to technological reasons. By modeling$F_{\max}$as a linear combination of the ring oscillators’ values, this paper employs Compressed Sensing theory to build the model and perform feature selection, enhancing model efficiency and interpretability. We explore regularized linear methods with convex/non-convex penalties in microcontroller performance screening, focusing on selecting informative ring oscillators. This permits reducing models’ footprint while retaining high prediction accuracy. Our experiments on two real-world microcontroller products compare Compressed Sensing with two alternative feature selection approaches: filter and wrapped methods. In our experiments, regularized linear models effectively identify relevant ring oscillators, achieving compression rates of up to 32:1, with no substantial loss in prediction metrics.

In safety-critical applications, microcontrollers must be compliant with the required quality constraints and performance standards, particularly in terms of the maximum operating frequency$(F_{\max })$. Machine learning (ML) models have proven effective in estimating$F_{\max }$by utilizing data extracted from on-chip ring oscillators (ROs), making them a valuable instrument for performance screening. However, the cost of obtaining labeled samples and the stringent accuracy needed by the model create hard challenges in this context. In order to address these, we explored three deep-learning (DL)-based key strategies: 1) semi-supervised learning with deep feature extractors: we leverage the abundance of unlabeled production data in a semi-supervised approach. Deep feature extractor models are employed to transform data into higher-dimensional spaces. These feature embeddings enable accurate performance prediction using simple linear regression, with a fraction of labeled data to reach baseline performances; 2) intrafamily transfer learning: when introducing new microcontroller products, with slightly different characteristics but the same set of ROs, previously trained deep feature extractors can be used, in a transfer learning fashion. This permits the use of significantly fewer labeled data compared to traditional methods; and 3) interfamily transfer learning: we extend the previous transfer learning concept to new microcontroller products with completely distinct characteristics. We aim to demonstrate that adapting the features set and fine-tuning DL feature extractors initially trained on specific legacy product data permits to yield better performance. Our research aims to provide a holistic framework for DL-based microcontroller performance screening to address the challenge of limited labeled data. The proposed methodologies significantly improve prediction accuracy and reduce the dependency on a large number of labeled samples, thus enhancing the efficiency and efficacy of ML-based microcontroller screening. The proposed framework enables models reuse, serving as a valuable baseline when new products are released.

In safety-critical applications, microcontrollers must meet strict quality and performance standards, including the maximum operating frequency$(F_{\max})$. Machine learning (ML) models can estimate$F_{\max}$using data from on-chip ring oscillators (ROs), making them suitable for performance screening. However, when new products are introduced, existing ML models may no longer be suitable and require updating. Training a new model from scratch is challenging due to limited data availability. Acquiring$F_{\max}$data is time-consuming and costly, resulting in a small labeled dataset. However, a large amount of data from legacy products may be available, along with existing ML models. In order to address the scarcity of labeled data, this paper proposes using deep learning feature extractors trained on specific MCU product data and fine-tuning them for new devices, in a Transfer Learning fashion. Experimental results show that these models can extract useful general features for performance prediction. As a result, they achieve better performance with significantly less labeled data compared to traditional shallow learning approaches.

In safety-critical applications, microcontrollers must satisfy strict quality constraints and performances in terms of Fmax(the maximum operating frequency). Data extracted from on-chip ring oscillators (ROs) can model the Fmaxof integrated circuits using machine learning models. Those models are suitable for the performance screening process. Acquiring data from the ROs is a fast process that leads to many unlabeled data. Contrarily, the labeling phase (i.e., acquiring Fmax) is a time-consuming and costly task, that leads to a small set of labeled data. This paper presents deep-learning-based methodologies to cope with the low number of labeled data in microcontroller performance screening. We propose a method that takes advantage of the high number of unlabeled samples in a semi-supervised learning fashion. We derive deep feature extractor models that project data into higher dimensional spaces and use the data feature embedding to face the performance prediction problem with simple linear regression. Experiments showed that the proposed models outperformed state-of-the-art methodologies in terms of prediction error and permitted us to use a significantly smaller number of devices to be characterized, thus reducing the time needed to build ML models by a factor of six with respect to baseline approaches.

In safety-critical applications, microcontrollers have to be tested to satisfy strict quality and performance constraints. It has been demonstrated that on-chip ring oscillators can be used as speed monitors to reliably predict the performances. However, any machine-learning (ML) model is likely to be inaccurate if trained on an inadequate dataset, and labeling data for training is quite a costly process. In this article, we present a methodology based on active learning to select the best samples to be included in the training set, significantly reducing the time and cost required. Moreover, since different speed measurements are available, we designed a multilabel technique to take advantage of their correlations. Experimental results demonstrate that the approach halves the training-set size, with respect to a random-labeling, while it increases the predictive accuracy, with respect to standard single-label ML models.

This paper encompasses three contributions by industry professionals and university researchers. The contributions describe different trends in automotive products, including both manufacturing test and run-time reliability strategies. The subjects considered in this session deal with critical factors, from optimizing the final test before shipment to market to in-field reliability during operative life.

In safety-critical applications, microcontrollers must satisfy strict quality constraints and performances in terms of $F_{\max}$, that is, the maximum operating frequency. It has been demonstrated that data extracted from on-chip speed monitors can model the $F_{\max}$ of integrated circuits by means of machine learning models, and that those models are suitable for the performance screening process. However, while acquiring data from these monitors is quite an accurate process, the labelling is time-consuming, costly, and may be subject to different measurements errors, impairing the final quality. This paper presents a methodology to cope with anomalous and noisy data in the context of the multi-label regression problem of microcontroller performance screening. We used outlier detection based on Inter Quartile Range (IQR) and Z-score and imputation techniques to detect errors in the labels and to avoid to drop incomplete samples, building higher-quality training set for our models, optimizing the devices characterization phase. Experiments showed that the proposed methodology increases the performance of existing models, making them more robust. These techniques permitted us to use a significantly smaller number of samples (about one third of the devices available for characterization), thus making the costly data acquisition process more efficient.

Speed monitors provide on-chip measurements of the the performance of integrated circuits. In recent years, they have been extensively used to predict Fmaxof microcontrollers for speed binning and performance screening during production test. However, while the use of machine learning is getting increasingly popular, the models may become significantly inaccurate if not trained on the appropriate devices. Previous research has demonstrated how to predict performance from speed-monitor data using corner-lot wafers. We show how to extend this approach to select the best corner-lot wafers to label when preparing the training set, thus significantly reducing the time and cost required for the process.