Early-stage timing analyses are essential for exploring design alternatives before physical synthesis in integrated circuit design, which needs to assess signal propagation delay multiple times with varying accuracy. Machine learning (ML) offers promising solutions for early-stage timing prediction, improving result quality while reducing runtime, time-to-market, and non-recurring engineering costs. However, existing ML-based approaches for predicting timing at the register-transfer level (RTL) are not sufficiently reliable to replace traditional electronic design automation tools as they face two key challenges: 1) feature generation based on high-level RTL is unreliable due to unpredictable synthesizer outputs, and 2) they omit essential features like technology library information and design constraints, which are crucial for accurate timing analysis.

Heterogeneous chiplet-based integration is expected to provide performance scalability and cost-effectiveness for the next generation of microelectronic systems. Practical deployment of chiplet-based platforms, however, requires developing novel electronic design automation (EDA) tools that support advanced packaging approaches. Compact thermal simulators are essential EDA tools for the evaluation of design alternatives at the early stages of the design. Developing efficient compact thermal simulators for advanced heterogeneous integration platforms is a key requirement, as the available tools provide limited support for heterogeneity and advanced packaging technologies. ARTSim 2.0, a robust thermal simulator for heterogeneous integration platforms, is presented in this work. ARTSim 2.0 includes three main features, i.e., robust hybrid meshing, modeling of heterogeneous layers, and an efficient solver that utilizes parallel processing. Several case studies on advanced chiplet-based platforms, including TSV-based 3-D integrated circuits (ICs), Intel EMIB, and TSMC InFO_PoP, are conducted to demonstrate the novel capabilities of ARTSim 2.0. The performance of ARTSim 2.0 for both transient and steady-state conditions is compared to results obtained from state-of-the-art finite element method (FEM) tools. Simulation results confirm that the temperature accuracy of the thermal maps that are generated by ARTSim 2.0 is within a maximum error of 1.17% while exhibiting a reduction in runtime of at least two orders of magnitude, as compared to the FEM tools.

Integrated power delivery methodology is a promising approach to achieve high power efficiency as the semiconductor industry targets higher power density and increased heterogeneity across different load characteristics. High quality and densely integrated passive devices are key components for the realization of integrated power delivery approaches.

The growing concern about offshore chip manufacturing has created considerable interest in solutions that can ensure the integrity and security of chips. Among various solutions, split manufacturing has received a lot of attention due to its security guarantees. With the recent emergence of new heterogeneous manufacturing technologies, including chiplet-based systems, there is a new opportunity for revisiting the design considerations for split manufacturing to fully exploit the opportunities presented by chiplet-based systems and improve various metrics, such as security, performance, and overhead.This work improves the state-of-the-art in secure chip manufacturing by proposing a new split manufacturing scheme. The key idea is to exploit the capabilities provided by chiplet integration technology for designing a new hybrid split manufacturing scheme that includes both vertical and horizontal splitting. Unlike existing vertical-only split manufacturing mechanisms, that target obfuscation of interconnections by splitting the design at a specific metallization layer into two portions, the proposed hybrid method increases trust by exploiting the chiplet paradigm shift, specifically, breaking the design into sub-designs, each represented by chiplets (independently fabricated), and obfuscating interconnections among them. The proposed obfuscation mechanism targets systems that exploit the chiplet technology to obtain important performance advantages, thus any chiplet-related overhead is not due to obfuscation. We evaluate our method using several experiments and compare it with the state-of-the-art using standard metrics, including area, power, delay, wirelength, and trust. Compared to conventional split manufacturing, our hybrid method achieves up to 245× higher trust, while exhibiting negligible overhead.

The inherent advantages of three-dimensional (3-D) integrated circuits (ICs) are well-aligned with the continuous demand for increased density of functionality, reduced latency, the power dissipation of communication, and heterogeneity of modern applications. Delivering power efficiently to highly heterogeneous voltage domains across the tiers of a 3-D IC is, however, a significant challenge. To address the power delivery challenge in 3-D ICs, a robust integrated power delivery methodology is proposed in this article. Recent advancements in the fabrication of high-density integrated passive components, and the area that is available in the vertical dimension of the 3-D construct, are exploited in this work to enable an efficient and robust power delivery system for 3-D ICs. In the proposed approach, one or more layers within the 3-D structure are dedicated to power conversion and regulation, namely, power layers (PLs). A design exploration stage is also provided to determine the number of PLs, distribution of resources between power and functional layers (FLs), assignment of voltage domains to PLs, and voltage levels across the power delivery system. The proposed methodology is compared to three other power delivery topologies and exhibits 1.4–$38\times $and 1.4–$7.1\times $improvement in, respectively, voltage drop and power efficiency. Results are normalized to the total on- and off-chip area dedicated to power conversion and regulation in each topology.

In recent years, with the rise of artificial intelligence and big data, there is an even greater demand for scaling out computing and memory capacity. Silicon interconnect fabric (Si-IF), a wafer-scale integration platform, promotes a paradigm shift in packaging features and enables ultra-large-scale systems, while significantly improving communication bandwidth and latency. Such systems are expected to dissipate tens of kilowatts of power. Designing an efficient and robust power delivery methodology for these high power applications is a key challenge in the enablement of the Si-IF platform. Based on several figure-of-merit parameters, an efficient power delivery methodology is matched with each of three candidate applications on the Si-IF, namely, artificial intelligence accelerators, high-performance computing, and neuromorphic computing. The proposed power delivery approaches were simulated and exhibit compatibility with the relevant ultra-large-scale application on Si-IF. The simulation results confirm that the dedicated power delivery topologies can support ultra-large-scale applications on the SI-IF.

Silicon interconnect fabric (Si-IF) is a wafer-scale heterogeneous integration platform. This platform promotes a paradigm shift in system integration and packaging methods, providing a single hierarchy of integration between the dies and the platform. The Si-IF effectively replaces the interposer, package, and printed circuit board. A power delivery methodology for high power wafer-scale systems (expected to dissipate up to 50 kW of power) is proposed in this paper. The proposed methodology includes three distinct power distribution topologies that are compared in terms of power loss, thermal consideration, and manufacturability. Compatible applications for each topology are also discussed. The electrical model, IR drop, and Ldi/dt noise, of each power distribution topology, are extracted and compared. Assuming a load voltage of 1 V, the three topologies exhibit a total voltage drop of, respectively, 16.68 mV, 9.62 mV, and 12.28 mV, corresponding to, respectively, 1.67%, 0.96%, and 1.23%. Hierarchical integration of decoupling capacitors is also described to ensure low voltage ripple (<; 5%) at the point of load. The electrical models of the power distribution topologies are verified using FEM and SPICE simulations.