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Zi Yu Xue

dblp:297/3201 · DBLP profile ↗
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5ranked-venue papers
1as first author
5since 2021 · last 2025
0000-0001-5236-2829ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 2 · 2 since 2021Systems, architecture and hardware · 2 · 1 first-author · 2 since 2021Applied, interdisciplinary, general and emerging computing · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Hardware accelerators and domain-specific architectures · 54% Memory systems · 37% Performance modeling and evaluation · 9%
Artificial intelligence
2 papers
Trustworthy machine learning · 61% Deep learning architectures and training · 21% Graph learning · 18%

Topics — the 8 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › sparsity exploitation
sparse tensor accelerator
1.522025
A Probabilistic Perspective on Tiling Sparse Tensor Algebra · MICRO 2025
Tailors: Accelerating Sparse Tensor Algebra by Overbooking Buffer Capacity · MICRO 2023
Machine learning › Trustworthy machine learning › interpretability
counterfactual explanation
0.512021
Robust Counterfactual Explanations on Graph Neural Networks · NeurIPS 2021
Machine learning › Trustworthy machine learning › interpretability › explanation evaluation
explanation robustness
0.512021
Robust Counterfactual Explanations on Graph Neural Networks · NeurIPS 2021
Machine learning › Graph learning
graph neural network
0.512021
Robust Counterfactual Explanations on Graph Neural Networks · NeurIPS 2021
Machine learning › Trustworthy machine learning
interpretability
0.512021
Robust Counterfactual Explanations on Graph Neural Networks · NeurIPS 2021
Performance modeling and evaluation
workload characterization
0.312025
A Probabilistic Perspective on Tiling Sparse Tensor Algebra · MICRO 2025
Memory systems › on-chip memory
on-chip buffer
0.212023
Tailors: Accelerating Sparse Tensor Algebra by Overbooking Buffer Capacity · MICRO 2023
Machine learning › Trustworthy machine learning
robustness
0.112021
Robust Counterfactual Explanations on Graph Neural Networks · NeurIPS 2021

Methods — techniques the papers use, named apart from their topics

traffic prediction · 0.9probability distribution model · 0.9design space search · 0.9tiling · 0.7data reuse optimization · 0.7label encoding · 0.6decision boundary modeling · 0.5counterfactual explanation generation · 0.5
YearPublicationVenuePosition
2025 A Probabilistic Perspective on Tiling Sparse Tensor Algebra
abstract
Sparse tensor algebra computations are often memory-bound due to irregular access patterns and low arithmetic intensity.We present D2T2 (Data-Driven Tensor Tiling), a framework that optimizes static coordinate-space tiling schemes to minimize memory traffic by identifying and leveraging relevant high-level statistics from input operands.For a given tensor algebra computation, D2T2 collects statistics from input tensors, builds a probability distribution-based model of the tensor computation, and uses it to predict traffic for various tiling configurations.It searches over tile shape and size configurations to minimize total traffic.We evaluate D2T2 against Tailors and DRT, two state of the art tiling schemes for sparse tensor algebra.We find that D2T2 achieves, on average, a 2.54× speedup over Tailors and a 1.13× lower memory bandwidth compared to DRT for sparse-sparse matrix multiplication (SpMSpM).We also achieve 1.22-48.94×lower bandwidth for SpMSpM and up to 34.31× lower bandwidth for tensor operations (TTM and MTTKRP) than conservative static tiling schemes.Unlike prior tiling techniques, D2T2 is deployable without specialized hardware support.On Opal, a 16nm sparse tensor algebra accelerator, D2T2 generated tiling configurations that achieve 1.23-3.34×speedups compared to their original hand-tuned configurations.
Ritvik Sharma, Zi Yu Xue, Nathan Zhang, Rubens Lacouture, Fredrik Kjolstad, Sara Achour, Mark Horowitz
MICRO2
2024 Characterizing and Improving Resilience of Accelerators to Memory Errors in Autonomous Robots
abstract
Motion planning is a computationally intensive and well-studied problem in autonomous robots. However, motion planning hardware accelerators (MPA) must be soft-error resilient for deployment in safety-critical applications, and blanket application of traditional mitigation techniques is ill suited due to cost, power, and performance overheads. We propose Collision Exposure Factor (CEF), a novel metric to assess the failure vulnerability of circuits processing spatial relationships, including motion planning. CEF is based on the insight that the safety violation probability increases with the surface area of the physical space exposed by a bit-flip. We evaluate CEF on four MPAs. We demonstrate empirically that CEF is correlated with safety violation probability and that CEF-aware selective error mitigation provides 12.3×, 9.6×, and 4.2× lower dangerous Failures-In-Time rate on average for the same amount of protected memory compared to uniform, bit-position, and access-frequency-aware selection of critical data. Furthermore, we show how to employ CEF to enable fault characterization using 23,000× fewer fault injection (FI) experiments than exhaustive FI and evaluate our FI approach on different robots and MPAs. We demonstrate that CEF-aware FI can provide insights on vulnerable bits in an MPA while taking the same amount of time as uniform statistical FI. Finally, we use the CEF to formulate guidelines for designing soft-error resilient MPAs.
Deval Shah, Zi Yu Xue, Karthik Pattabiraman, Tor M. Aamodt
ACM Trans. Cyber Phys. Syst.2
2023 Tailors: Accelerating Sparse Tensor Algebra by Overbooking Buffer Capacity
abstract
Sparse tensor algebra is a challenging class of workloads to accelerate due to low arithmetic intensity and varying sparsity patterns. Prior sparse tensor algebra accelerators have explored tiling sparse data to increase exploitable data reuse and improve throughput, but typically allocate tile size in a given buffer for the worst-case data occupancy. This severely limits the utilization of available memory resources and reduces data reuse. Other accelerators employ complex tiling during preprocessing or at runtime to determine the exact tile size based on its occupancy.
Zi Yu Xue, Yannan Nellie Wu, Joel S. Emer, Vivienne Sze
MICRO1
2022 Label Encoding for Regression Networks
Deval Shah, Zi Yu Xue, Tor M. Aamodt
ICLR2
2021 Robust Counterfactual Explanations on Graph Neural Networks
abstract
Massive deployment of Graph Neural Networks (GNNs) in high-stake applications generates a strong demand for explanations that are robust to noise and align well with human intuition. Most existing methods generate explanations by identifying a subgraph of an input graph that has a strong correlation with the prediction. These explanations are not robust to noise because independently optimizing the correlation for a single input can easily overfit noise. Moreover, they are not counterfactual because removing an identified subgraph from an input graph does not necessarily change the prediction result. In this paper, we propose a novel method to generate robust counterfactual explanations on GNNs by explicitly modelling the common decision logic of GNNs on similar input graphs. Our explanations are naturally robust to noise because they are produced from the common decision boundaries of a GNN that govern the predictions of many similar input graphs. The explanations are also counterfactual because removing the set of edges identified by an explanation from the input graph changes the prediction significantly. Exhaustive experiments on many public datasets demonstrate the superior performance of our method.
Mohit Bajaj, Lingyang Chu, Zi Yu Xue, Jian Pei 0001, Lanjun Wang, Peter Cho-Ho Lam, Yong Zhang 0004
NeurIPS3