Yuya Isaka

dblp:298/5809 · DBLP profile ↗
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2ranked-venue papers
2as first author
2since 2021 · last 2024
0000-0001-7839-4247ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author · 2 since 2021Software engineering, systems software and programming languages · 2 · 2 first-author · 2 since 2021
YearPublicationVenuePosition
2024 EcoFlex-HDP: High-Speed and Low-Power and Programmable Hyperdimensional-Computing Platform with CPU Co-Processing
abstract
Hyperdimensional computing (HDC) can efficiently perform various cognitive tasks efficiently by mapping data to hyperdimensional vectors with thousands to tens of thousands of dimensions. However, the primary operations of HDC—Bind, Permutation, and Bound—need to be executed more efficiently on a standard CPU platform. This study introduces a novel computational platform, EcoFlex-HDP, specifically designed for HDC. EcoFlex-HDP exploits the parallelism and high memory access efficiency of HDC operations to achieve low computation time and energy consumption, outperforming the CPU. Furthermore, it can work cooperatively with a CPU, enabling integration with existing software, providing flexibility to apply new algorithms, and contributing to the development of an HDC ecosystem. Through experimental evaluations with a Cortex-A9 processor, HDC operations were shown to be accelerated by a maximum of 169 times. Furthermore, EcoFlex-HDP was confirmed to improve the energy-delay product by up to 13,469 times when training an image recognition task. All source codes for our platform and experiments are available at https://github.com/yuya-isaka/EcoFlex-HDP.
Yuya Isaka, Nau Sakaguchi, Michiko Inoue, Michihiro Shintani
DATE1
2021 Unsupervised Recycled FPGA Detection Based on Direct Density Ratio Estimation
abstract
With the expansion of the semiconductor supply chain, recycled field-programmable gate arrays (FPGAs) have become a serious concern. Several methods for detecting recycled FPGAs by analyzing the ring oscillator (RO) frequencies have been proposed; however, most assume the presence of known fresh FPGAs (KFFs) as the training data used for machine-learning-based classification, which is an impractical assumption. In this study, we propose a novel KFF-free recycled FPGA detection method based on an unsupervised anomaly detection scheme. As the RO frequencies in the neighboring logic blocks on an FPGA are similar because of systematic process variation, our method compares the RO frequencies and does not require KFFs. The proposed method efficiently identifies recycled FPGAs through outlier detection using direct density ratio estimation. Experiments using Xilinx Artix-7 FPGAs demonstrate that the proposed method successfully distinguishes two recycled FPGAs from 10 fresh FPGAs. In contrast, a conventional KFF-free recycled FPGA detection method results in certain misclassification.
Yuya Isaka, Foisal Ahmed, Michihiro Shintani, Michiko Inoue
IOLTS1