Approximate computing is an emerging paradigm for error-tolerant applications. By introducing a reasonable amount of inaccuracy, both the area and delay of a circuit can be reduced significantly. To produce approximate circuits automatically, many approximate logic synthesis (ALS) algorithms are proposed. However, they mainly focus on area reduction and are not optimal in reducing the circuit delay. In this article, we propose HEDALS, a Highly Efficient Delay-driven ALS framework, which supports various types of local approximate changes (LACs), circuit representations, and average error metrics. To reduce delay, HEDALS builds a critical error graph (CEG) consisting of nodes on the critical paths and error information, and finds an optimized set of LACs in the CEG by either a maximum flow-based method or a priority cut-based method. The resulting set of LACs is applied to shorten all critical paths simultaneously so that the circuit delay is reduced. Besides, the simultaneous application of multiple LACs also makes HEDALS extremely fast. Compared to a state-of-the-art method, on average, HEDALS can reduce the circuit delay by 32.3%, while being$167\times $faster. The code of HEDALS is made open-source.

The Internet of Things (IoT) is a new heterogeneous system integrated by the various end users (sensors and terminals) with different technologies. However, the limiting factor is bandwidth in the IoT due to the exploding end users and the network bandwidth requirements. A novel IoT model, which integrates the power-line carrier (PLC) and the wireless network (WN), is proposed to solve the bandwidth problem from the architecture, especially in the areas lacking network facilities. In addition, we exploit an effective virtual layer (EVL) which allows the different end users to access the system model seamlessly. Then, the attractor selection algorithm based on Markov chain (MASA) is employed to select an optimal path among the PLC or WN. The simulation results demonstrate that the proposed system model has the smaller average queuing delay than other algorithms and makes the model more stable and robust.

Approximate computing is an emerging paradigm for error-tolerant applications. By introducing a reasonable amount of inaccuracy, both the area and delay of a circuit can be reduced significantly. To synthesize approximate circuits automatically, many approximate logic synthesis (ALS) algorithms have been proposed. However, they mainly focus on area reduction and are not optimal in reducing the delay of the circuits. In this paper, we propose DALS, a delay-driven ALS framework. DALS works on the AND-inverter graph (AIG) representation of a circuit. It supports a wide range of approximate local changes and some commonly-used error metrics, including error rate and mean error distance. In order to select an optimal set of nodes in the AIG to apply approximate local changes, DALS establishes a critical error network (CEN) from the AIG and formulates a maximum flow problem on the CEN. Our experimental results on a wide range of benchmarks show that DALS produces approximate circuits with significantly reduced delays.

Approximate computing is an emerging design paradigm targeting at error-tolerant applications. The area, delay, and power consumption of a circuit can be improved by sacrificing a reasonable amount of accuracy. Approximate logic synthesis (ALS) aims at automatically synthesizing an approximate circuit for a given target circuit. In this paper, we propose to approximate a target function by a maximally disjoint bi-decomposable function, which can significantly reduce the implementation cost. We propose novel techniques to effectively generate such an approximation with low error rate. We further integrate this approximation technique into a systematic ALS flow. Experiment results show the effectiveness of our proposed ALS flow in producing approximate circuits with reduced areas.