Airborne Base Stations (ABSs) allow for flexible geographical allocation of network resources with dynamically changing load as well as rapid deployment of alternate connectivity solutions during natural disasters. Since the radio infrastructure is carried by unmanned aerial vehicles (UAVs) with limited flight time, it is important to establish the best location for the ABS without exhaustive field trials. This paper proposes a digital twin (DT)-guided approach to achieve this goal through the following key contributions: (i) Implementation of an interactive software bridge between two open-source DTs such that the same scene is evaluated with high fidelity across NVIDIA's Sionna and Aerial Omniverse Digital Twin (AODT), highlighting the unique features of each of these platforms for this allocation problem, (ii) Design of a back- propagation-based algorithm in Sionna for rapidly converging on the physical location of the UAVs, orientation of the antennas and transmit power to ensure efficient coverage across the swarm of the UAVs, and (iii) numerical evaluation in AODT for large network scenarios (50 UEs, 10 ABS) that identifies the environmental conditions in which there is agreement or divergence of performance results between these twins. Finally, (iv) we propose a resilience mechanism to provide consistent coverage to mission-critical devices and demonstrate a use case for bi-directional flow of information between the two DTs.

As Fifth generation (5G) cellular systems transition to softwarized, programmable, and intelligent networks, it becomes fundamental to enable public and private 5G deployments that are (i) primarily based on software components while (ii) maintaining or exceeding the performance of traditional monolithic systems and (iii) enabling programmability through bespoke configurations and optimized deployments. This requires hardware acceleration to scale the Physical (PHY) layer performance, programmable elements in the Radio Access Network (RAN) and intelligent controllers at the edge, careful planning of the Radio Frequency (RF) environment, as well as end-to-end integration and testing. In this paper, we describe how we developed the programmable X5G testbed, addressing these challenges through the deployment of the first 8-node network based on the integration of NVIDIA Aerial RAN CoLab Over-the-Air (ARC-OTA), OpenAirInterface (OAI), and a near-real-time RAN Intelligent Controller (RIC). The Aerial Software Development Kit (SDK) provides the PHY layer, accelerated on Graphics Processing Unit (GPU), with the higher layers from the OAI open-source project interfaced with the PHY through the Small Cell Forum (SCF) Functional Application Platform Interface (FAPI). An E2 agent provides connectivity to the O-RAN Software Community (OSC) nearreal-time RIC. We discuss software integration, network infrastructure, and a digital twin framework for RF planning. We then profile the performance with up to 4 Commercial Off-the-Shelf (COTS) smartphones for each base station with iPerf and video streaming applications, as well as up to 25 emulated User Equipments (UEs), measuring a cell rate higher than 1.65 Gbps in downlink and 143 Mbps in uplink.

Fast sector-steering in the mmWave band for vehicular mobility scenarios is a challenge because standard-defined exhaustive search over predefined antenna sectors cannot be assuredly completed within short contact times. This paper proposes machine learning to speed up sector selection using data from multiple non-RF sensors, such as LiDAR, GPS, and camera images in the mmWave radios with large codebooks. The contributions in this paper are threefold: First, we propose a multimodal deep learning architecture that fuses the inputs from these data sources and locally predicts the sectors for best alignment at a vehicle. Second, we propose FLASH-and-Prune, which combines the knowledge from multiple vehicles by aggregating the local model parameters and exploits model pruning to optimize the model parameter exchange overhead. Third, we present a pruning strategy that takes into account the distributed nature of federated learning to adaptively prune or retrieve model weights. We validate the proposed architecture on a real-world multimodal dataset collected from an autonomous car. We observe that FLASH-and-Prune incurs 29.25% and 35.89% less overhead in the uplink and downlink, respectively, compared to standard federated learning.

Even though machine learning (ML) techniques are being widely used in communications, the question of how to train communication systems has received surprisingly little attention. In this paper, we show that the commonly used binary cross-entropy (BCE) loss is a sensible choice in uncoded systems, e.g., for training ML-assisted data detectors, but may not be optimal in coded systems. We propose new loss functions targeted at minimizing the block error rate and SNR deweighting, a novel method that trains communication systems for optimal performance over a range of signal-to-noise ratios. The utility of the proposed loss functions as well as of SNR deweighting is shown through simulations in NVIDIA Sionna.

We propose a multiple-input multiple-output (MIMO) detector based on an annealed version of the underdamped Langevin (stochastic) dynamic. Our detector achieves state-of-the-art performance in terms of symbol error rate (SER) while keeping the computational complexity in check. Indeed, our method can be easily tuned to strike the right balance between computational complexity and performance as required by the application at hand. This balance is achieved by tuning hyperparameters that control the length of the simulated Langevin dynamic. Through numerical experiments, we demonstrate that our detector yields lower SER than competing approaches (including learning-based ones) with a lower running time compared to a previously proposed overdamped Langevin-based MIMO detector.

Solving the optimal symbol detection problem in multiple-input multiple-output (MIMO) systems is known to be NP-hard. Hence, the objective of any detector of practical relevance is to get reasonably close to the optimal solution while keeping the computational complexity in check. In this work, we propose a MIMO detector based on an annealed version of Langevin (stochastic) dynamics. More precisely, we define a stochastic dynamical process whose stationary distribution coincides with the posterior distribution of the symbols given our observations. In essence, this allows us to approximate the maximum a posteriori estimator of the transmitted symbols by sampling from the proposed Langevin dynamic. Furthermore, we carefully craft this stochastic dynamic by gradually adding a sequence of noise with decreasing variance to the trajectories, which ensures that the estimated symbols belong to a pre-specified discrete constellation. Based on the proposed MIMO detector, we also design a robust version of the method by unfolding and parameterizing one term– the score of the likelihood– by a neural network. Through numerical experiments in both synthetic and real-world data, we show that our proposed detector yields state-of-the-art symbol error rate performance and the robust version becomes noise-variance agnostic.

We consider an integrated access and backhaul (IAB) node operating in full-duplex (FD) mode. We analyze simultaneous transmission from the New Radio gNB to the IAB node on the backhaul uplink, IAB node to a user equipment (UE) on the access downlink, and IAB transmitter to the IAB receiver on the self-interference (SI) channel. Our contributions include (1) a low complexity algorithm to jointly design the hybrid analog/digital beamformers for all three nodes to maximize the sum spectral efficiency of the access and backhaul links by canceling SI and maximizing received power; (2) derivation of all-digital beamforming and spectral efficiency upper bound for use in benchmarking; and (3) simulations to compare full vs. half duplex modes, hybrid vs. all-digital beamforming algorithms, proposed hybrid vs. conventional beamforming algorithms, and spectral efficiency upper bound. In simulations, the proposed algorithm shows significant reduction in SI power and increase in sum spectral efficiency.

Blindly decoding a signal requires estimating its unknown transmit parameters, compensating for the wireless channel impairments, and identifying the modulation type. While deep learning can solve complex problems, digital signal processing (DSP) is interpretable and can be more computationally efficient. To combine both, we propose the dual path network (DPN). It consists of a signal path of DSP operations that recover the signal, and a feature path of neural networks that estimate the unknown transmit parameters. By interconnecting the paths over several recovery stages, later stages benefit from the recovered signals and reuse all the previously extracted features. The proposed design is demonstrated to provide 5% improvement in modulation classification compared to alternative designs lacking either feature sharing or access to recovered signals. The estimation results of DPN along with its blind decoding performance are shown to outperform a blind signal processing algorithm for BPSK and QPSK on a simulated dataset. An over-the-air software-defined-radio capture was used to verify DPN results at high SNRs. DPN design can process variable length inputs and is shown to outperform relying on fixed length inputs with prediction averaging on longer signals by up to 15% in modulation classification.

Deep learning has been recently applied to many problems in wireless communications including modulation classification and symbol decoding. Many of the existing end-to-end learning approaches demonstrated robustness to signal distortions like frequency and timing errors, and outperformed classical signal processing techniques with sufficient training. However, deep learning approaches typically require hundreds of thousands of floating points operations for inference, which is orders of magnitude higher than classical signal processing approaches and thus do not scale well for long sequences. Additionally, they typically operate as a black box and without insight on how their final output was obtained, they can't be integrated with existing approaches. In this paper, we propose a novel neural network architecture that combines deep learning with linear signal processing typically done at the receiver to realize joint modulation classification and symbol recovery. The proposed method estimates signal parameters by learning and corrects signal distortions like carrier frequency offset and multipath fading by linear processing. Using this hybrid approach, we leverage the power of deep learning while retaining the efficiency of conventional receiver processing techniques for long sequences. The proposed hybrid approach provides good accuracy in signal distortion estimation leading to promising results in terms of symbol error rate. For modulation classification accuracy, it outperforms many state of the art deep learning networks.

We propose a new, low-complexity data-detection algorithm and a corresponding high-throughput FPGA design for 3GPP LTE-based large-scale (or massive) multi-user (MU) multiple-input multiple-output (MIMO) wireless communication systems. Our algorithm performs approximate minimum mean-square error (MMSE) data detection using coordinate descent (CD), which enables near-MMSE performance at low computational complexity, even for systems with hundreds of antennas at the base station (BS). We design a high-throughput VLSI architecture for 3GPP LTE wideband systems with a deep and interleaved pipeline, which can be parametrized at design time to support various antenna configurations. Our CD-based data detector achieves 379Mb/s throughout, while using 24 k LUTs and 771 DSP units on a Xilinx Virtex-7 FPGA for a 128 BS antenna, 8 user large-scale MU-MIMO system.

This paper describes a step forward in the utilization of non-maximally decimated filter banks (NMDFBs) with perfect reconstruction (PR) property in modern software defined radios. In particular, here we apply the tone reservation (TR) technique for reducing the peak to average power ratio (PAPR) to a PR analysis-synthesis chain which has been designed for a combined Third Generation Partnership Protocol (3GPP), Long Term Evolution (LTE) and Universal Mobile Telecommunications System (UMTS) digital up converter (DUC). The DUC architecture was proposed in an early paper and the efficacy of the design has been tested in an industrial environment and verified for being prototyped on real chips. Similar to orthogonal frequency division multiplexing (OFDM) systems, the proposed architecture is affected by the PAPR issue. Here we borrow the TR reservation technique which was developed in the OFDM scenario and we apply it to the proposed architecture. Of course, given the difference between OFDM and NMDFB systems, different design constraints have to be taken into account. Preliminary simulation results show good performance in reducing the crest factor (CF) which, along with the limited workload required by the proposed architecture, encourage us to implement this solution in the next generation of communication chips.

This paper proposes - to the best of our knowledge - the first ASIC design for high-throughput data detection in single carrier frequency division multiple access (SC-FDMA)-based large-scale MIMO systems, such as systems building on future 3GPP LTE-Advanced standards. In order to substantially reduce the complexity of linear soft-output data detection in systems having hundreds of antennas at the base station (BS), the proposed detector builds upon a truncated Neumann series expansion to compute the necessary matrix inverse at low complexity. To achieve high throughput in the 3GPP LTE-A uplink, we develop a systolic VLSI architecture including all necessary processing blocks. We present a corresponding ASIC design that achieves 3.8 Gb/s for a 128 antenna, 8 user 3GPP LTE-A based large-scale MIMO system, while occupying 11.1 mm2in a TSMC 45nm CMOS technology.

There are number of software defined radio applications in which a radio receiver must access multiple simultaneous channels with different channel bandwidths. This paper presents the architecture of a novel and extremely efficient implementation of such a channelizer. The receiver described here simultaneously forms ten 5-MHz wide channels and one hundred 0.5 MHz wide channels spanning a 50 MHz input bandwidth. Multirate signal processing techniques are used throughout the processing chain to obtain extremely low processing computational workload.

In this paper, we analyze the VLSI implementation tradeoffs for linear data detection in the uplink of large-scale multiple-input multiple-output (MIMO) wireless systems. Specifically, we analyze the error incurred by using the sub-optimal, low-complexity matrix inverse proposed in Wu et al., 2013, ISCAS, and compare its performance and complexity to an exact matrix inversion algorithm. We propose a Cholesky-based reference architecture for exact matrix inversion and show corresponding implementation results on an Virtex-7 FPGA. Using this reference design, we perform a performance/complexity trade-off comparison with an FPGA implementation for the proposed approximate matrix inversion, which reveals that the inversion circuit of choice is determined by the antenna configuration (base-station antennas vs. number of users) of large-scale MIMO systems.

The high processing complexity of data detection in the large-scale multiple-input multiple-output (MIMO) uplink necessitates high-throughput VLSI implementations. In this paper, we propose - to the best of our knowledge - first matrix inversion implementation suitable for data detection in systems having hundreds of antennas at the base station (BS). The underlying idea is to carry out an approximate matrix inversion using a small number of Neumann-series terms, which allows one to achieve near-optimal performance at low complexity. We propose a novel VLSI architecture to efficiently compute the approximate inverse using a systolic array and show reference FPGA implementation results for various system configurations. For a system where 128 BS antennas receive data from 8 single-antenna users, a single instance of our design processes 1.9M matrices/s on a Xilinx Virtex-7 FPGA, while using only 3.9% of the available slices and 3.6% of the available DSP48 units.

We present an experiment-based characterization of passive suppression and active self-interference cancellation mechanisms in full-duplex wireless communication systems. In particular, we consider passive suppression due to antenna separation at the same node, and active cancellation in analog and/or digital domain. First, we show that the average amount of cancellation increases for active cancellation techniques as the received self-interference power increases. Our characterization of the average cancellation as a function of the self-interference power allows us to show that for a constant signal-to-interference ratio at the receiver antenna (before any active cancellation is applied), the rate of a full-duplex link increases as the self-interference power increases. Second, we show that applying digital cancellation after analog cancellation can sometimes increase the self-interference, and thus digital cancellation is more effective when applied selectively based on measured suppression values. Third, we complete our study of the impact of self-interference cancellation mechanisms by characterizing the probability distribution of the self-interference channel before and after cancellation.

We show that efficient implementation of codebook-based beamforming Multiple Input Single Output (MISO) systems with good performance is feasible in the presence of channel-induced imperfections (due to imperfect channel estimate and feedback delay) and implementation-induced imperfections (due to real-world radio hardware effects). To present our results, we adopt a mixed approach of analytical, simulation, and experimental evaluation. Our analytical and simulation results take into account channel-induced imperfections but do not take into account implementation-induced imperfections (which are difficult to model in a tractable way). Thus, we complement these results with experimental results that do take into account both channel and implementation-induced imperfections. This mixed approach provides a more complete picture of expected performance. As part of our study we develop a framework for Average Error Vector Magnitude Squared (AEVMS)-based analysis of beamforming MISO systems which facilitates comparison of analytical, simulation, and experimental results on the same scale. In addition, AEVMS allows fair comparison of experimental results obtained from different wireless testbeds. We derive novel expressions for the AEVMS of beamforming MISO systems and show how the AEVMS relates to important system characteristics like the diversity gain, coding gain, and error floor.

In this paper, we present the architecture of a highly configurable multi-input multi-output (MIMO) orthogonal frequency division multiple access (OFDMA) platform. The platform is designed to support experimentation with various communication algorithms, thus allowing an intimate understanding of the performance of complex algorithms under real-life constraints. The hardware used is the wireless open access research platform (WARP) which facilitates rapid prototyping utilizing the FPGA and multi radio interfaces available.

K-best MIMO detection technique is the prominent method of simplifying the detection complexity in MIMO systems while maintaining BER performance comparable with the optimum maximum-likelihood (ML) detection technique. However, sorting the candidate nodes in the tree search of the conventional K-best detection can take a significant number of cycles which would reduce the achievable data rate of the detector. In order to reduce this delay, and keep high performance at the same time, we propose using a novel sort-free based MIMO detector which avoids the demanding sorting step. Moreover, this detector utilizes a novel modified real-valued decomposition (M-RVD) ordering that, when compared to the conventional real valued decomposition scheme, can improve the BER performance at no extra computational cost. We show that our proposed detector can outperform the conventional K-best detector with a smaller combination of computation and latency requirements.

This paper addresses the problem of peak to average power ratio (PAPR) reduction in multi-band transmitters. Transmitter linearity requirements are addressed and trade-off analysis for design and optimization of the PAPR reduction algorithm within the context of the error vector magnitude (EVM) and adjacent channel leakage ratio (ACLR) quality metrics are studied. Our study also includes mapping of the signal processing algorithms onto Xilinx Virtex-4trade field programmable gate array (FPGA) technology and addresses the device resource utilization and efficient hardware implementation of the above PAPR reduction algorithms onto the above mentioned device. Statistical simulations and performance assessments of the proposed algorithms are presented

This paper addresses the problem of crest factor reduction (CFR) in multi-carrier WCDMA systems. A trade-off analysis for design and optimization of the PAPR reduction algorithm within the context of the error vector magnitude (EVM) and adjacent channel leakage ratio (ACLR) quality metrics are studied. Statistical characteristics of the clipping noise are analyzed and a novel method for clipping the multi-band signal under the phase invariant constraint is proposed. Our study also includes mapping of the signal processing algorithms onto Xilinx Virtex-4TMfield programmable gate array (FPGA) technology and addresses the device resource utilization and efficient hardware implementation of the above PAPR reduction algorithms onto the above mentioned device. Statistical simulations and performance assessments of the proposed algorithms are presented.

A digitally controlled sampled data delay line is implemented with recursive all-pass filter sections. This is in marked contrast to the standard implementation of programmable time delays that use fixed non-recursive polyphase stages or adjustable Farrow FIR filters. The recursive filter exhibits an equal-ripple approximation to constant group delay. The phase slope is programmable to present a continuously variable time delay network. Applications of a continuously adjustable, linear- time delay structure offers unique signal processing options to address various communication system tasks. These include timing recovery in DSP and FPGA based receivers, adaptive beam forming and steering, communication systems channel modeling, and reverberation modeling in acoustic chambers and instruments.

Digital signal processing techniques are applied to maximum likelihood carrier phase synchronization for QPSK and QAM in an all-digital sampled data receiver. To achieve the flexibility required by modern software defined radios (SDRs), this task must either be performed in a DSP processor (reconfigurable software) or in an FPGA (reconfigurable hardware). This paper describes the design process for an FPGA-based design and summarizes the FPGA resources required for QPSK carrier phase synchronization.

Software defined radios (SDR) are highly configurable hardware platforms that provide the technology for realizing the rapidly expanding third (and future) generation digital wireless communication infrastructure. Many sophisticated signal processing tasks are performed in a SDR, including advanced compression algorithms, power control, channel estimation, equalization, forward error control and protocol management. While there is a plethora of silicon alternatives available for implementing the various functions in a SDR, field programmable gate arrays (FPGAs) are an attractive option for many of these tasks for reasons of performance, power consumption and configurability. Amongst the more complex tasks performed in a high data rate wireless system is synchronization. This paper is about carrier and timing synchronization in SDRs using FPGA based signal processors. We describe and examine a QPSK Costas loop for performing coherent demodulation, and report on the implications of an FPGA mechanization. Symbol timing recovery is addressed using a differential matched filter control system. A tutorial style approach is adopted to describe the operation of the timing recovery loop and considerations for FPGA implementation are outlined.

No abstract available.

This paper investigates an architectural option for constructing high sample-rate narrow-band single rate and multi-rate filters using Xilinx field programmable gate array (FPGA) technology. Sigma-delta modulation encoding is applied to the input data in order to effect a reduction in the precision of the arithmetic units in the filter. This is done without compromising the signal integrity within the band of interest. The implementation provides a significant savings in device logic resources in comparison to other techniques that provide the same functionality. The sigma-delta preprocessor is described and its implementation using XC4000 FPGAs is reported. The architecture of the reduced precision filter is presented and its FPGA realization described.

No abstract available.