Utilization of the Delay-Doppler (DD) domain enables the recently proposed two-dimensional (2D) Orthogonal Time Frequency Space (OTFS) waveform to provide consistent performance under high mobility communication systems. OTFS outperforms existing standard waveforms under such time-frequency selective channels, making it a waveform candidate for future wireless communication systems. In this work, we present an implementation of an OTFS waveform-based system on a Universal Software Radio Peripheral (USRP) X310 Software Defined Radio (SDR). This system is tested in a realistic indoor office environment at a 5 GHz carrier frequency band with 150 MHz bandwidth. The resulting constellation diagrams were observed for BPSK, 4-QAM, and 16-QAM modulated OTFS symbols. Furthermore, for 4-QAM symbols, several communication metrics, such as Bit Error Rate (BER) and Error Vector Magnitude (EVM), were evaluated against different gains at the USRP. The resulting constellation diagrams, BER, and EVM graphs show a successful implementation of our OTFS system.

The rapid growth of high-precision location-based services (LBSs), has driven indoor localization as a key research area in recent years. The transition towards higher frequency bands, such as millimeter wave (mmWave), enables high-precision localization for future wireless technologies. By deploying a diverse set of positioning techniques, we can further mitigate the limitations of single measurement position estimation, resulting in a more robust user localization and tracking system. This also enhances the design of positioning systems that support different levels of accuracy. In this work, we use a particle filter to combine the time difference of arrival (TDoA) and angle of arrival (AoA) measurements in the mmWave band for a more accurate position estimate. In addition, we evaluate the performance of the proposed algorithm by examining the positioning performance with that of the individual measurements using the least square (LS) method and hybrid measurements using the weighted least square (WLS) method. The simulation results show that the proposed hybrid particle filter (PF)-based algorithm improves the positioning accuracy by 23.9% compared to that of the hybrid WLS-based method. The combination of the hybrid TDoA and AoA measurements results in a mean positioning error of 17.4 cm.

In this paper, we investigate the effectiveness of a newly proposed frame superposition Hybrid Automatic Repeat reQuest (HARQ) scheme, which adopts different variants of spatially coupled low-density parity-check (LDPC) codes. The construction of the method with the use of 5 G new radio (NR) LDPC codes is explained in detail. Bit error rate (BER), frame error rate (FER), and the projected data goodput in additive white Gaussian noise (AWGN) and Rayleigh block fading channels are investigated. The HARQ scheme is based on frame combination by using spatially coupled LDPC codes. It outperforms all classical variants of HARQ and can, hence, be seen as a potential successor of the classical methods. The main cost is the need for more complicated LDPC decoding, whereby the decoder needs to support the decoding of two or even more blocks at the same time.

Localization will be an essential requirement for various$6^{\text{th}}$generation (6G) communication system applications. Integrated Sensing and Communication (ISAC) is seen as a key enabling technology that can provide the capability of combined communication and localization. Reliable ISAC in a high-mobility environment can be challenging and existing communication waveforms suffer from severe degradation due to significant Doppler effect. The Delay-Doppler (DD) domain can be commonly seen in the results of Radio Detection and Ranging (RADAR) systems, which is the baseline for Orthogonal Time Frequency Space (OTFS) modulation. Due to the information encoding in DD domain, OTFS shows significant resilience against doubly-selective channels. In this work, we report the sensing functionality performance of our complete sub-6GHz ISAC system based on the OTFS waveform, implemented on a USRP X310 Software Defined Radio (SDR). The sensing capability of the system is experimentally verified in both an anechoic chamber and in an office scenario for single and for multitargets.

With new technological advancements in wireless communication, reflected in 3GPP (Third Generation Partnership Project) cellular or wireless local area network (WLAN) standards, increasing data rate is a prominent aspect. Consequently, some backhaul networks require a data rate in the order of 100 gigabits per second. The D-Band, which can provide ample bandwidth, potentially can support this data rate. This paper analyzes the line-of-sight D-Band multiple input multiple output (MIMO) channel for different antenna arrangements, which are best suited for achieving the nearly orthogonal channels for exploiting MIMO full-rank spatial multiplexing. This allows for flexibility in antenna arrangement design in hardware, which is not limited to uniform linear or rectangular arrays. We have also addressed the impact of the transmitter array orientation and provided an algorithm to compensate for the misalignment by estimating the orientation and mechanically re-aligning the receiver array in that direction. Furthermore, a general simplified communication link is numerically simulated, showing that tilt significantly impacts equalizer performance and overall spectral efficiency, and the compensation algorithm is able to restore system performance effectively. Additionally, by comparing different antenna arrangements, it is found that a triangular antenna arrangement has exceptional performance over a range of antenna spacing. Unlike other antenna arrangements, that require optimum antenna spacing, it does not require optimum but tolerates a range of deviations with little practical impact on system performance.

Indoor localization has attracted considerable attention in recent years, driven by the growth of Internet of Things (IoT) applications. The transition of wireless communication systems toward higher frequency bands has further enabled higher accuracy user positioning. Various positioning methods have emerged over the years, supporting different levels of accuracy. In this work, we leverage measurements from multiple wireless communication technologies to address a dynamic positioning scenarios. We employ a Particle Filter (PF) to combine Time-of-Arrival (ToA) estimates from Sub-6 GHz and mmWave technology to enhance the localization accuracy in an indoor environment. Additionally, we evaluate the performance of the proposed algorithm by examining the positioning error statistics in different scenarios. Simulation results indicate that the proposed hybrid algorithm improves the mean localization and tracking error by approximately 42.8% and 17.8%, in comparison to the individual use of Sub-6 GHz and mmWave positioning technologies, respectively. The combination of these estimates results in a mean absolute positioning error better than 10 cm.

In this paper, we propose an improved Hybrid Automatic Repeat reQuest (HARQ) scheme based on cross-packet superposition retransmission by employing dedicated low-density parity-check (LDPC) matrices. Simulation results demonstrate that the scheme improves Bit Error Rate (BER) and Packet Error Rate (PER) performance up to 0.4 dB at the cost of increased packet handling complexity. The key element of our system is the combination of the systematic part of a codeword with the parity part of another codeword without any reductions in the code rate. Thus, to some extent, retransmission can be performed without any need to send additional parity bits.

This paper presents a millimeter-wave (mmWave) integrated communication and sensing (ICAS) system with softwaredefined radio (SDR) that can support two-stream multiple-input multiple-output (MIMO) communication and mono- as well as bi-static sensing. The system consists of a ZCU111 evaluation board with a high-performance radio-frequency system-on-chip (RFSoC) field-programmable gate array (FPGA) and two 60 GHz dual antenna beamforming modules. The SDR design comprises 4 digital-to-analogue and 4 analogue-to-digital converters with dedicated memories and a programmable sampling frequency in the 160-4000 MHz range with 160 MHz step-size. The RF frontends support an instantaneous bandwidth of up to 2 G H z, and a 90° horizontal beam scan. The sensing function is demonstrated using a typical frame-based orthogonal frequency division multiplexing (OFDM) communication signal. A range resolution of 6.7 cm and an angular resolution of 1.45° is achieved.

The performance of practical millimetre wave (mmWave) communication systems is affected by different hardware impairments. This can significantly impact the channel reciprocity-based physical layer security (PLS) methods. This paper studies the impact of in-and quadrature-phase (IQ) imbalance on the physical layer secure key generation algorithm performance. Numerical analysis is performed in MATLAB by modelling and simulating the IQ imbalance, which is then applied to the 60 GHz channel used to generate secret keys. The study's outcome shows that IQ imbalance increases bit mismatches up to an average of 5% for an amplitude imbalance of 1.4 dB and a phase imbalance of 7°. However, additional iterations of parity bit sequence exchanges can recover these in the reconciliation phase. As a result, the information is slightly more exposed to an eavesdropper.

RADAR-based gesture recognition has attracted a lot of attention in recent years. A large number of studies have been conducted on single RADAR-based gesture recognition. However, there is still a lot of space to explore multi-RADAR-based gesture recognition. Compared to a single-RADAR scenario, a multi-RADAR scenario can provide higher stability and recognition performance. In the context of the multi-RADAR scenario, an efficient, high-performance algorithm is proposed in this paper for the purpose of extracting features from RADAR data and classifying gestures using a simple machine-learning model. The experimental results demonstrate a high average recognition rate of 97.78% on the test set with the proposed algorithm and model, and a significant reduction in runtime compared to the reference work. This can be a very promising application in joint communication and sensing (JCAS) system.

This paper introduces the concept of optimizing beam training at the medium access control (MAC) layer by employing passive sensing. The environment information can be extracted from the channel state information (CSI) when data frames are received. The delay and angle of arrival (AoA) parameters are estimated assuming an orthogonal frequency-division multiple (OFDM) system operating in the 60 GHz band. A method for enhancing the communication performance on the MAC layer by using sensing information from multiple wireless transceivers is proposed.

Extremely high frequency millimeter wave communication systems are essential for future wireless systems to address the continuous growth in data traffic. Reliable beam tracking is imperative to reduce the beam training overhead generated during the beam re-alignment phase in mobility scenarios. In this paper, we propose a beam tracking algorithm assisted by high-precision user position information estimated using multiple technologies. The proposed algorithm is based on particle filter algorithm, which leverages location information, gathered on a localization server to accelerate the beam tracking process. The simulation results show that the proposed approach has an improved mean square error of angle of arrival estimation of around 58% as compared to the conventional mmWave technology positioning-aided beam tracking. The tracking performance of the proposed algorithm is improved at higher antenna array sizes and lower angle variances.

This paper proposes modifications for the parallel sequence spread spectrum (PSSS) modulation scheme, which improve the bit error rate (BER) performance and peak-to-average power ratio (PAPR) at the same time. In our scheme, some data bits are encoded as phase shifts of the spreading sequences. Thus, the number of transmitted sequences can be reduced, and the resulting PAPR is lowered. The improvements proposed here are inspired by code shift keying (CSK) and parallel combinatory spread spectrum (PCSS) systems. The PSSS variant investigated here is based on recently discovered real-value spreading sequences, where all sequence coefficients are defined in the real domain.

Human-computer interaction using radar has gained a lot of attention. Gesture recognition with a single Frequency Modulated Continuous Wave (FMCW) radar has been investigated by many researchers, and several promising results have been achieved. However, the stability of such a system still needs to be improved. This paper proposes a signal-processing approach for gesture recognition based on multiple FMCW radars.VGG16 pre-trained model is employed to extract features from the dataset, after which gesture recognition is performed using a Support Vector Machine (SVM) classifier and an XGBoost classifier, respectively. Moreover, the effect of the incomplete dataset in case of failure of one of the radars on the accuracy of gesture recognition is also analysed. The experimental results show that the SVM classifier in the multiple radar scenario obtains up to 96.67% accuracy on the test set, which is 1.78% to 5.95% higher than the single radar scenario. In the multi-radar scenario, when the extracted dataset is incomplete, the SVM classifier achieves up to 95% recognition accuracy. This proves that multi-radar is more stable than the single radar scheme. This system can be applied in smart homes, in-car entertainment systems or smart factories.

Low-Density Parity-Check (LDPC) and polar codes are two classes of channel codes potentially able to achieve the channel capacity, and both are used in current 5G communication systems. Belief Propagation (BP), which is the main decoding algorithm for LDPC codes could also be used for decoding polar codes. A fully parallel fully unrolled BP decoding architecture has been recently proposed for both of these codes. In this paper, we investigate these two architectures further and compare the two codes from the viewpoint of Bit-Error Rate (BER) performance, achieved throughput, latency, chip area, and also energy efficiency. Toward that, both architectures have been synthesized in a 28 nm CMOS technology, and corresponding results are provided.

Polar codes are one of the candidates as a Forward-Error Correction (FEC) scheme for next-generation high-throughput communication systems. Successive Cancellation (SC) is one of the main decoding algorithms for decoding polar codes. In this paper, a fully pipelined fast Simplified SC (SSC) decoding architecture is proposed which proves a throughput of 1542 Gb/s in a 28 nm CMOS ASIC technology. This architecture is fully pipelined in the sense that sequences are decoded successively in consecutive clock cycles. The implementation results after the design Place&Route show improvements in terms of decoding throughput, clock frequency, core area, and energy efficiency compared with the state-of-the-art.

Belief Propagation (BP) algorithm is an alternative decoding method to Successive Cancellation (SC) decoding of polar codes with an advantage of higher throughput and lesser latency. BP algorithm is performed over the factor graph of a polar code, and its throughput is oppositely proportional to the number of stages of the factor graph. The stage-combining idea can be applied to the factor graph of a polar code to halve the number of stages, and thus to double the decoding throughput. By this idea, every two adjacent stages of a factor graph are combined and processed in a single step. In this paper, we propose a modified stage-combined BP decoding method that is able to improve the Bit-Error Rate (BER) performance of the decoding algorithm. This improvement is almost 0.5 dB at low to intermediate SNRs, and much more considerable at high SNRs, since the undesired phenomenon of error floor is mitigated as a result of the proposed stage-combining mechanism.

This paper proposes an optimized pipelined decoding architecture with seven processing stages for unrolled LDPC decoders. Pipelined design with seven register layers significantly increases the resulting clock frequency. Moreover, we investigate the optimal layout shape for unrolled decoders. This paper's fastest decoder is based on the IEEE 802.11n LDPC(1944,1620) parity-check matrix and achieves 2937 Gb/s of coded throughput after physical design. By optimizing the pipeline, floorplan, and employing a codeword length of 1944 bits, we increased the throughput by 241% compared to the previous fastest LDPC decoder presented in the literature. To the best of our knowledge, it is the fastest soft-decision decoder published so far. The standard min-sum approach is employed for decoding, and the proposed improvements consider changes only on the hardware level.

This paper compares three hardware variants of successive cancelation (SC) decoders for polar codes. The fastest implementation, based on the basic SC, provides decoding throughput up to 1700 Gb/s, when implemented in a 28 nm CMOS technology at the worst-case timing corner. This is the fastest polar decoder published so far, to the best of our knowledge. We also discuss the difficulties of implementing single-parity-check nodes and repetition nodes in fast simplified SC (Fast-SSC) decoding algorithm. These two node types are the primary sources of clock frequency reduction, and special care needs to be taken when these elements are implemented. The Fast-SSC decoder requires ~3 times fewer hardware resources than the base version of SC, but achieves ~10% lower decoding throughput.

Polar codes have been proved to be able to achieve the capacity of a Binary-Input Discrete Memoryless Channel (B-DMC) despite the possibility of a low-complexity encoding and decoding. Belief Propagation (BP) decoding is one of the major techniques proposed and vastly used for decoding polar codes, which has the advantage of high throughput compared with the other main decoding technique, namely Successive Cancellation (SC). The number of iterations in BP decoding is of utmost importance, as it directly impacts decoding performance, throughput, and power consumption. Devising an appropriate criterion for early termination of decoding once the remaining iterations are not necessary is therefore a useful technique for preventing further latency and power consumption. In this paper, an H-matrix-based criterion for early termination is introduced and shown to be more effective than the conventional G-matrix-based technique without sacrificing the Bit-Error Rate (BER) performance. It is also argued that the proposed method is simpler to be implemented, and its complexity is further reduced as the code-rate increases, unlike the G-matrix criterion whose complexity grows as the code-rate increases.

This paper reports our latest implementation results of a fully unrolled LDPC decoder prototyped in 28 nm CMOS technology. The decoder achieves 1218 Gbps coded throughput and consumes a 5.49 mm2chip area. The standard min-sum decoding algorithm with four-bit quantization, five unrolled iterations, (648,540) parity matrix, and a seven-stage pipeline is employed. Such implementation achieves a higher data rate than adaptive degeneration and finite-alphabet decoding algorithms, requires less silicon than the solutions mentioned above, and is fully compliant with the IEEE 802.11n WLAN standard.

Hand gesture recognition driven by RADAR technology has attracted significant attention in recent years. Among various RADAR types, frequency-modulated continuous-wave (FMCW) RADAR is used in this work due to its very high range and velocity resolution. However, data collected by RADAR are disturbed by static background and static clutter. Therefore, a novel data preprocessing approach is proposed to remove the static background and clutter in the acquired data. A convolutional neural network is used to extract the features of the acquired data set. To the best of our knowledge, this is the first time that range, velocity and angle features are combined in one map, forming the input signal of a convolutional neural network. Classifiers are applied to recognize gestures. Experimental results show that the proposed method using the XGBoost classifier can achieve a high recognition accuracy of 98.93% on the test set. In contrast, the proposed method with the random forest classifier can achieve a recognition rate of 100% on the same test set with six dynamic hand gestures. This approach could be useful in aspects such as in-car entertainment systems and smart homes.

In this work, we propose a Deep neural network-assisted Particle Filter-based (DePF) approach to address the Mobile User (MU) joint synchronization and localization (sync&loc) problem in ultra-dense networks. In particular, DePF deploys an asymmetric time-stamp exchange mechanism between the MUs and the Access Points (APs), which, traditionally, provides us with information about the MUs’ clock offset and skew. However, information about the distance between an AP and an MU is also intrinsic to the propagation delay experienced by the exchanged time-stamps. In addition, to estimate the angle of arrival of the received synchronization packets, DePF draws on the multiple signal classification algorithm that is fed with the Channel Impulse Response (CIR) experienced by the sync packets. The CIR is also leveraged to determine the link condition, i.e. Line-of-Sight (LoS) or Non-LoS. Finally, to perform joint sync&loc, DePF capitalizes on particle Gaussian mixtures that allow for a hybrid particle-based and parametric Bayesian Recursive Filtering (BRF) fusion of the aforementioned pieces of information and, thus, jointly estimates the position and clock parameters of the MUs. The simulation results verify the superiority of the proposed algorithm over the state-of-the-art schemes, especially that of the extended Kalman filter- and linearized BRF-based joint sync&loc. In particular, only drawing on the synchronization time-stamp exchange and CIRs from a single AP, for 90% of the cases, the absolute position and clock offset estimation error remain below 1 meter and 2 nanoseconds, respectively.

We propose a closed-loop industrial radio system with a star topology for factory automation using Parallel Sequence Spread Spectrum (PSSS) technology. This system implements all significant concepts for synchronization, duplex-communication, channel estimation/equalization based on an innovative transceiver concept. The industrial environment tends to have non-line of sight channels that lead to RMS delay spreads of less than 100 ns. Here, we propose a channel equalization scheme to compensate for these delay spreads. Another challenging aspect is the implementation of a code division duplexing (CDD) scheme. We propose a closed-loop system architecture that can achieve the targets set by Industry 4.0 bodies such as IWSAN. This paper gives an overview of the closed-loop systems concept.

This paper investigates coding and modulation schemes for wireless communication based on variable-rate parallel sequence spread spectrum (PSSS). PSSS can adapt the spreading gain according to channel conditions. When this modulation technique is combined with external forward error correction (FEC), a challenge arises in adjusting the gains from FEC and PSSS to achieve the highest spectral and energy efficiency. We profile the bit error rate (BER) and energy efficiency as a function of the signal-to-noise ratio (SNR) for PSSS combined with low-density parity-check (LDPC) codes implemented in 28 nm CMOS technology. This analysis reveals that the gain provided by PSSS should be used only in exceptional cases, whereas LDPC codes provide the gain at a lower spectral- penalty. Moreover, we simplify our system by reducing the number of LDPC code rates. As compared to IEEE 802.11n, we exclude the 2/3 and 3/4 FEC code rates from the hardware and compensate these modes by using the variable-rate PSSS.

This paper investigates chip area, clock frequency, throughput, power consumption, and energy efficiency of real-valued spreading sequences proposed for Parallel Sequence Spread Spectrum (PSSS). On the one hand, real-valued sequences cause significant hardware overhead when compared to the usually employed binary m-sequences. On the other hand, these sequences achieve 2.5 dB better signal-to-noise ratio (SNR) performance in PSSS systems. The experiments performed on the test designs implemented in a 28 nm CMOS technology reveal that the real-valued sequences, up to the length of 17 bits, cause low hardware overhead and allow processing data streams up to 400 Gbps. Longer sequences can break the barrier of 1 Tbps, but this is paid with a large chip area and extremely high power consumption. In the case of a 1 Tbps PSSS system, power dissipation is the main critical parameter in need of optimization.

In this paper, we investigate the mean communication rate loss (MCRL) due to beam cusping with respect to multiple input multiple output (MIMO) spatial dimensions, beamforming codebook sizes, and beam scan spaces for beamforming operations controlled by the medium access control (MAC) layer beamforming protocol. The intractability of the analytical investigation for a closed-form expression leads to the usage of Monte Carlo numerical experiments. For discrete Fourier transform (DFT) beamforming codebooks, the MCRL increases with an increase in the MIMO dimensions while it decreases with an increase in the beam scan space from the array broadside. The MCRL becomes negligible as the number of beams for selection is increased to four times the number of DFT beams. These results will be helpful for determination of MIMO configuration, angular coverage zone, codebook size, and phase-shifter resolution for a minimal MCRL. This is especially relevant for sparse MIMO channels of millimetre-wave (mmWave) and terahertz (THz) wireless systems in the fifth generation (5G) and beyond mobile networks.

Spread spectrum clocking (SSC) conventionally uses frequency modulation (FM) to suppress digital switching noise in the frequency domain. While clock-FM effectively reduces spectral noise peaks, it maintains the synchronous operation per cycle with total noise unchanged. In this paper, we introduce plesiochronous design as a general applicable de-synchronization solution for the spectral switching noise optimization with guaranteed quality-of-service. By modeling on-chip aperiodic supply current as a poly-cyclostationary random process, we theoretically prove that digital plesiochronous design contributes to reducing both, total and peak switching noise, in a harmonic frequency band of interest logarithmically proportional to the number of adopted clock domains over the synchronous baseline. A complete framework is also developed to implement plesiochronous design with the optimal clock domain partitioning and FIFO-based synchronization that features a minimum depth of six by employing Johnson encoding fully compatible with mainstream design flow. Validated on a 130nm pipelined FFT test chip across 25 dies thus taking process variations into account, our plesiochronous SSC achieves on average 5.1dB total power reductions in addition to 12.8dB peak power reductions of substrate noise at the clock fundamental frequency, which match our predictions, with only marginal hardware overhead in terms of cell area and power consumption.

In this work, we study the joint synchronization and localization (sync&loc) of Mobile Nodes (MNs) in ultra dense networks. In particular, we deploy an asymmetric time-stamp exchange mechanism between the MNs and the Access Nodes (ANs), that, traditionally, provides us with information about the MNs' clock offset and skew. However, information about the distance between an AN and a MN is also intrinsic to the propagation delay experienced by exchanged time-stamps. In addition, we utilize Angle of Arrival (AoA) estimation to determine the incoming direction of time-stamp exchange packets, which gives further information about the MNs' location. Finally, we employ Bayesian Recursive Filtering (BRF) to combine the aforementioned pieces of information and jointly estimate the position and clock parameters of the MNs. The simulation results indicate that the Root Mean Square Errors (RMSEs) of position and clock offset estimation are kept below 1 meter and 1 nanosecond, respectively.

In this work, we propose a hybrid Bayesian approach towards clock offset and skew estimation, thereby synchronizing large scale networks. In particular, we demonstrate the advantage of Bayesian Recursive Filtering (BRF) in alleviating time-stamping errors for pairwise synchronization. Moreover, we indicate the benefit of Factor Graph (FG), along with Belief Propagation (BP) algorithm in achieving high precision end-to-end network synchronization. Finally, we reveal the merit of hybrid synchronization, where a large-scale network is divided into local synchronization domains, for each of which a suitable synchronization algorithm (BP- or BRF-based) is utilized. The simulation results show that, despite the simplifications in the hybrid approach, the Root Mean Square Errors (RMSEs) of clock offset and skew estimation remain below 5 ns and 0.3 ppm, respectively.

This paper presents novel radio frequency (RF) beam training algorithms for sparse multiple-input multiple-output (MIMO) channels using unitary RF beamforming codebooks at transmitter (Tx) and receiver (Rx). The algorithms leverage the statistical knowledge from memory-based past beam training data for expedited massive MIMO channel-learning with statistically-minimal training overheads. Beams are tested in the order of their ranks based on their probabilities for providing a communication link. For low beam entropy scenarios, statistically-ranked beam search performs excellent in reducing the average number of beam tests per Tx-Rx beam pair identification for a communication link. For high beam entropy cases, a hybrid RF beam training algorithm involving both memory-assisted statistically-ranked (MarS) beam search and multi-level (ML) beam search is also proposed. Savings in training overheads increase with decrease in relative beam entropy and increase in MIMO channel dimensions. A novel mathematical operation of multiplying the elements of a Kronecker product with their respective position numbers in the Kronecker product vector is also brought out which may find further applications in the future.

Millimeter wave (mmWave) communication has emerged as a key technology for achieving high data throughput and low latency in 5G networks. Thanks to the large channel bandwidths in the mmWave spectrum (e.g. 2.16 GHz in the 57-66 GHz band), mmWave technology allows precise and accurate time of flight (ToF) measurements, hence supporting precise and accurate positioning. In this paper, an experimental evaluation of ToF-based localization in the 60 GHz band is presented. We implemented the two-way ranging (TWR) protocol between a mobile node and multiple anchor nodes. The implementation is carried out on an own software-defined radio (SDR) baseband platform, combined with commercial 60 GHz chipsets. Tests were performed indoors in a laboratory environment. The results of our evaluation show that a positioning error of less than 5 cm can be obtained.

In this paper, we obtain and study typical beam entropy values for millimetre-wave (mm-wave) channel models using the NYUSIM simulator for frequencies up to 100 GHz for the fifth generation (5G) and beyond 5G cellular communication systems. The beam entropy is used to quantify sparse MIMO channel randomness in beamspace. Lower relative beam entropy channels are suitable for memory- assisted statistically-ranked (MarS) and hybrid radio frequency (RF) beam training algorithms. High beam entropies can potentially be advantageous for low overhead secured radio communications by generating cryptographic keys based on the channel randomness in beamspace, especially for sparse multiple-input multiple- output (MIMO) channels. Urban microcell (UMi) and urban macrocell (UMa) cellular scenarios have been investigated in this work for 28, 60, 73, and 100 GHz carrier frequencies and the rural macrocell (RMa) scenario for 3.5 GHz.

In this paper, we show a novel algorithm for strong line-of-sight (LoS) multiple-input-multiple-output (MIMO) channel equalization. With optimally spaced antennas under specific arrangements, the LoS channels can be made spatially orthogonal. In practice, antenna displacements are expected. Conventional algorithms like zero-forcing (ZF) do not consider the special properties of the LoS MIMO channel and result in high complexity. We show that the LoS MIMO channel can be factorized into a product of three matrices. Thereby, the two diagonal matrices at the outer product positions are the most varying terms and should be compensated dynamically. Being a good tradeoff between complexity and robustness, the proposed sequential channel equalization is applied in a reverse order of the factorization. The algorithm can be applied to LoS MIMO systems with uniform linear or rectangular arrays, which are making use of digital or analog equalization. By considering the usage of the Winograd butterfly and Butler matrices, the number of multiplications in both digital and analog implementations of the proposed solution is increasing approximately linearly with respect to the number of antennas, while the complexity of the state-of-the-art designs grows quadratically. As found numerically and verified experimentally, the proposed method performs nearly as well as the ZF-based algorithms with near-optimal arrangements, while having significantly lower complexity.

With large bandwidths, millimeter wave (mmWave) line-of-sight (LoS) multi-input multi-output (MIMO) technology employing parallel stream transmission is well suited for future wireless backhaul systems. However, hardware imperfections of mmWave transceivers cause additional signal processing challenges. Considering the channel and hardware properties, this paper proposes a novel frame structure with high temporal efficiency. The required MIMO processing can be decomposed into two steps. The first one removes the interantenna interference including the carrier frequency offsets. In the second step, the intersymbol interference brought by the frequency-selective components is canceled with a parallel structure. As a comparison, a more general decision-directed least-mean-square approach (DD-LMS) for joint processing of all effects is introduced. With a 60 GHz 2 × 2 LoS MIMO demonstrator, only the widely linear version of DD-LMS achieves performance of about 0.2-0.6 dB better than the proposed method but requires approximately four times more complexity. The proposed method with parallel processing chains is well suited especially for larger LoS MIMO systems, e.g., for a system with 16 streams, its required complexity is less than 7% of the widely linear DD-LMS.

In this paper we present measurement results for pure line-of-sight MIMO links operating in the millimeter wave range. We show that the estimated condition numbers and capacities of the measured channels are in good agreement with the theory for various transmission distances and antenna setups. Furthermore, the results show that orthogonal channel vectors can be observed if the spacing criterion is fulfilled, thus facilitating spatial multiplexing and achieving high spectral efficiencies even over fairly long distances. Spacings generating ill-conditioned channel matrices show on the other hand significantly reduced performance.

Applications based on precise indoor and urban area localization are becoming quite popular. The integration of localization in currently existing wireless data communication systems is especially interesting. The popularity comes from the possibility to economically use the same analog front-end for data communication and localization. In indoor environments, where the precision should be under 1 m, because of the limited sample rate of the A/D converters, range binning becomes the main source of errors. Noise is not so much a problem, because for systems used mainly in indoor scenarios, the SNR is usually quite good. One solution, which is used to mitigate range binning is oversampling. Since oversampling requires additional hardware complexity, we propose here a “modified equivalent time sampling” approach. With this approach, no oversampling data converters are needed. The same data converters used for data communication can be used for ranging, but some signal processing before transmission and after reception of the signal is needed. The achieved resolution of the distance measurements is comparable to the solution with oversampling data converters.

Globally asynchronous locally synchronous (GALS) design has attracted intensive research attention during the last decade. Among the existing GALS design solutions, the pausible clocking scheme presents an elegant solution to address the cross-clock synchronization issues with low hardware overhead. This work explored the applications of pausible clocking scheme for area/power efficient GALS design. To alleviate the challenge of timing convergence at the system level, area and power balanced system partitioning was applied for GALS design. An optimized GALS design flow based on the pausible clocking scheme was further proposed. As a practical example, a synchronous/GALS OFDM baseband transmitter chip, named Moonrake, was then designed and fabricated using the 40-nm CMOS process. It is shown that, compared to the synchronous baseline design, 5% reduction in area and 6% saving in power can be achieved in the GALS counterpart.

After motivating asynchronous techniques in general, the main advantages and disadvantages will be discussed. Several asynchronous timing models such as delay insensitive (DI) quasi delay insensitive (QDI) and speed independent (SI) will be presented and compared. Completion-detection methods used in asynchronous design are reviewed.

In this paper, a trade-off analysis between concatenated codes consisting of a convolutional (CC) followed by a Reed-Solomon (RS) code versus low-density parity-check (LDPC) codes is presented. The analysis is based on a twofold criterion: coding gain for a target bit error rate (BER) of 10-6and required decoder hardware complexity for a target data throughput of 10 Gbps. Furthermore, we have investigated relevant parameters which directly impact an efficient hardware implementation as well as the error correction performance of the LDPC decoder. These parameters include an attenuation factor in the min-sum layered (MSL) decoding algorithm, the finite word length of soft information and an early-termination (ET) strategy. The error correction performances are evaluated for 16-QAM modulation over an independent Rayleigh fading channel. The complexity of the RS-CC and LDPC decoders is estimated based on synthesis results using an Infineon 40 nm CMOS design kit.

With the growth in complexity of digital CMOS circuits, the steep current fluctuations introduced by numerous transistors switching with clock signals are proven to be a significant source of electromagnetic interference (EMI). In recent years the reduction in EMI noise from high speed digital ICs has already gained intensive research attention. In this paper the pausible clocking based globally asynchronous locally synchronous (GALS) design with phase and frequency modulation on the locally generated clocks is proposed as a systematic solution to EMI reduction. As a practical example, a 64-point Radix-23pipelined GALS FFT processor was implemented using the IHP 130nm CMOS technology for low-EMI applications. The on-chip measurements demonstrate 13dB attenuation at the clock fundamental frequency and more than 20dB attenuation at higher clock harmonics, in comparison with the synchronous design.

This paper presents the developed 60-GHz OFDM hardware demonstrators and the newly designed 60-GHz system architecture targeting for multi-gigabit wireless LAN applications. The hardware demonstrators developed so far are made up of maximum 1-Gbps OFDM baseband realized on FPGA platform and 60-GHz super-heterodyne transceivers fabricated by SiGe BiCMOS technologies. Wireless transmission in 60-GHz links is successfully demonstrated in indoor office environments. The next generation 60-GHz OFDM systems are designed to provide data rate higher than 3-Gbps utilizing the channel bandwidth of 2.16-GHz. Advanced channel coding schemes including low-density-parity-check (LDPC) coding are applied to have higher coding gain. RF transceivers are based on sliding IF architecture and designed to be compatible to the channel plans defined in the 60-GHz standards.

This paper describes a millimetre-wave receiver beamforming for interference mitigation as well as array gain enhancement. Like the beamforming architecture in the IEEE 802.15.3c standard, it is based on only one baseband processor to support multiple N-element antenna arrays for low-cost implementation. This makes it difficult to estimate received signals and channel state information on each antenna, which restricts baseband digital processing and introduces large overheads for adaptive beamforming. For these reasons, the IEEE 802.15.3c standard utilizes 2-bit beam codebook for repetitive beam-searching, however it cannot offer adaptive interference nulling capability. We propose an algorithm to get received signal information on each antenna so that we can find optimum weight vectors for maximum beamforming gain. This also enables to mitigate co-channel interference, which increase total throughput by enhancing spatial re-use in multiple 60-GHz indoor networks. The structural difference from the IEEE 802.15.3c beamformer is to employ a continuous phase-shifter, however our implementation proves that it exhibits almost same-level complexity as 2-bit phase-shifters.

In this paper, we undertake a comparison of LDPC (768,384) and convolutional (171,133) codes for 60-GHz OFDM-based wireless communication systems. The comparison is based on two parameters: Frame Error Rate (FER) for 60-GHz channels and decoding hardware complexity for a required throughput of more than 1 Gbps. Additionally, we provide performance parameters of a fully parallel LDPC decoder chip, fabricated in our IHP in-house 0.13 μm CMOS technology, achieving a throughput of more than 1 Gbps.

In this paper, we present a non-coherent differential binary phase-shift keying demodulation scheme with a 1-bit analogue-digital-converter, based on a novel likelihood-decoding scheme. It needs very little resources in both, the analogue and the digital domain. This is useful for simple receivers operating under frequency-flat channel conditions. The demodulation scheme was integrated in a complete transceiver based on a FPGA platform connected to a 60 GHz analogue frontend. In addition to the presented simulations, we measured the real system behavior in an office environment and showed a stable HD video transmission over a 60 GHz line-of-sight link.

Pausible clocking based globally-asynchronous locally-synchronous (GALS) system design has been proven a promising approach to SoCs and NoCs. In this paper, we analyze the throughput reduction and synchronization failures introduced by the widely used pausible clocking scheme, and propose an optimized scheme for higher throughput and more reliable GALS design. The local clock generator is improved to minimize the acknowledge latency, and a novel input port is applied to maximize the safe timing region for the clock tree insertion. Simulation results using the IHP 0.13-µm standard CMOS process demonstrate that up to one-third increase in data throughput and an almost doubled safe timing region for clock tree distribution can be achieved in comparison to the traditional pausible clocking scheme.

In this paper, we present implementation details of the digital front end of a wideband OFDM baseband receiver. This receiver offers datarates up to 1.08 GBit/s using a channel bandwidth of 400 MHz. The full baseband has been successfully implemented and tested on a FPGA platform running at a clock speed of only 100 MHz. It is part of a complete 60 GHz demonstrator including MAC, PHY and analog front end. In addition, we give performance results under realistic radio link assumptions for the 480 MBit/s mode to demonstrate the efficiency of the algorithms.

We present new Gbps orthogonal frequency division multiplexing (OFDM) physical layers and performance evaluations for applications of 60-GHz wireless local area network (WLAN). They are designed to operate in 57-66 GHz unlicensed frequency band with the possibility to use different channel bandwidth and to promise full compatibility to the channel plan that most 60-GHz standard groups have employed. Different modulation and coding schemes given by the designed OFDM physical layers allow scalable spectral efficiency to provide different payload data rates with different radio coverage. To facilitate practical hardware implementation with the designed OFDM physical layers, the performance evaluations are done with realistic 60-GHz channel models and 60-GHz nonideal RF front-ends models. The results confirm that the designed OFDM physical layer is suitable for high-data rate wireless LAN systems in practical application scenarios.

We present 60 GHz OFDM hardware demonstrators developed so far and outline design considerations for future developments. OFDM schemes have been developed to combat multi-path interferences in indoor wireless environments and further optimized for multi-gigabit data transmission in 60 GHz-band. RF and IF analogues front-ends (AFEs) have been developed with high-speed SiGe BiCMOS technologies. Future developments on AFE are mainly devoted to one-chip integration of RF and IF components based on a sliding IF architecture. We have already achieved wireless transmission of about 1 Gbps in an OFDM demonstrator, which will be continuously upgraded and optimized for higher data transmission with better link adaptability.

This paper describes a pragmatic approach on the up-conversion of WiMedia compliant UWB signals into the 60 GHz band. This dual band concept is based on propagation measurements at {3.1-10.6} and 60 GHz. Due to stringent frequency regulation, UWB systems operating in the 3.1 to 10.6 GHz bands are both bandwidth limited and power limited. Therefore, many potential users hesitate to deploy this technology. Up-conversion to the 60 GHz band and enhanced baseband parameters can make UWB technology more reliable and hence, more attractive. An experimental system based on a commercially available UWB development kit and IHPpsilas 60 GHz chip-set has been developed. The system architecture is described. Measurement results indicate that this combination may be interesting for many applications.

Millimeter wave wireless communications are opening the way towards high data rate applications for WPAN scenarios. Multi-Gbps wireless systems are currently defined by standardization bodies. This paper presents a complete 60 GHz OFDM PHY layer proposal fulfilling the requirements of the IEEE 802.15 Task Group 3c. Data rates are ranging from 335 Mbps to 3 Gbps, with a high level of scalability. The proposed system is designed to operate in the 57 to 66 GHz frequency band, with a possibility to use channel sizes of 1 GHz and 2 GHz. The OFDM PHY layer allows scalable spectrum efficiency to achieve high data rates with flexible radio coverage. For a nominal channel bandwidth of 1 GHz, the system uses an FFT size of 1024, convolutional coding and advanced interleaving schemes. Simulation results show that this system is well suited for very high data rate applications in realistic scenarios.

This paper reports implementation details of a 60 GHz short range communication system for data rates up to 2 Gbit/s. Based on a MATLAB model the main PHY parameters were derived, and the modules of the analog frontend were specified. For system verification, a demonstrator was developed. The analog RF and IF circuits of the demonstrator are implemented in a 0.25 μm SiGe BiCMOS technology. Measurement results of the analog modules and the complete demonstrator are given. Using OFDM modulation, the maximum data rate transmitted via airlink so far, is 960 Mbit/s.

We devise a low-complexity synchronization and channel estimation scheme intended for future 60 GHz wireless personal area networks (WPANs). We show through simulation that a good frame detection rate and good synchronization performance is achieved even for relatively high phase noise.

In this article we propose a complete solution for the so-called inner receiver of an OFDM-WLAN system based on the IEEE 802.11a standard. We concentrate our investigations on three key components forming the inner receiver namely, the synchronizer, the channel estimator and the digital timing loop. The main goal is the joint optimization of the signal processing algorithms along with the implementation friendly VLSI architecture required for these three key components in order to reduce power, area and latency, without compromising the performance excessively. We provide both the mathematical details and extensive computer simulations to validate our design

In this paper a test technique based on the built-in self-test (BIST) is proposed. Our BIST concept is based on hierarchical testing of the digital systems. The presented test scheme is optimized for globally asynchronous locally synchronous (GALS) systems. The BIST technique, described here, is implemented on a GALS baseband processor compliant to the IEEE 802.11a standard. Some results on the performance of our test solution are given. The GALS processor with embedded BIST was fabricated in IHP's 0.25 /spl mu/m CMOS technology and test results are presented.

In this paper, we proposed a novel Coordinate Rotation Digital Computer (CORDIC) rotator algorithm that converges to the final target angle by adaptively executing appropriate iteration steps while keeping the scale factor virtually constant and completely predictable. The new feature of our scheme is that, depending on the input angle, the scale factor can assume only two values, viz., 1 and 1//spl radic/2, and it is independent of the number of executed iterations, nature of iterations, and word length. In this algorithm, compared to the conventional CORDIC, a reduction of 50% iteration is achieved on an average without compromising the accuracy. The adaptive selection of the appropriate iteration step is predicted from the binary representation of the target angle, and no further arithmetic computation in the angle approximation datapath is required. The convergence range of the proposed CORDIC rotator is spanned over the entire coordinate space. The new CORDIC rotator requires 22% less adders and 53% less registers compared to that of the conventional CORDIC. The synthesized cell area of the proposed CORDIC rotator core is 0.7 mm/sup 2/ and its power dissipation is 7 mW in IHP in-house 0.25-/spl mu/m BiCMOS technology.

We propose a novel 16-bit low power CORDIC rotator that is used for high-speed wireless LAN. The algorithm converges to the final target angle by adaptively selecting appropriate iteration steps while keeping the scale factor virtually constant. The VLSI architecture of the proposed design eliminates the entire arithmetic hardware in the angle approximation datapath and reduces the number of iterations by 50% on an average. The cell area of the processor is 0.7 mm and it dissipates 7 mW power at 20 MHz frequency.

The authors propose a low-power synchronizer design for the IEEE 802.11a standard capable to estimate frequency offsets in the range /spl plusmn/468 kHz (80 ppm @ 5.8 GHz) with very simple and effective frame detection and timing synchronization. The core area of the design after layout is 13 mm/sup 2/, including the CORDIC and FFT processors, with a total estimated power consumption of 140 mW.

A novel 64-point FFT/IFFT processor is presented in this article, named TURB064, developed primarily for the application for the IEEE 802.11 (a) standard. The processor does not use any digital multiplier or RAM. It has been fabricated and tested successfully. Its core area is 6.8 mm/sup 2/ and the average power consumption is 41 mW at 1.8 V @ 20 MHz frequency. Compared to some other existing IP cores and ASIC chips TURB064 needs a smaller number of clock cycles and consumes less power.