VLDB 2026 Research / reviewers in the wild / expert
Murali R. Varanasi
dblp:30/3041
· DBLP profile ↗
6ranked-venue papers
1as first author
0since 2021 · last 2010
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 1 first-authorComputer networks · 2Artificial intelligence and machine learning · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Artificial intelligence
1 paper |
Motion planning and robot control · 70% Robot manipulation · 30% | |
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Hardware reliability and fault tolerance · 100% | |
| Theoretical computer science
1 paper |
Coding theory · 100% |
Topics — the 11 heaviest of 12, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware reliability and fault tolerance › error correction
error-correcting codes |
0.0 | 2 | 1990 | Unidirectional Byte Error Detecting Codes for Computer Memory Systems · IEEE Trans. Computers 1990 Code Constructions for Error Control in Byte Organized Memory Systems · IEEE Trans. Computers 1983 |
Robotics › Motion planning and robot control
collision detection |
0.0 | 1 | 1988 | Collision detection for planning collision-free motion of two robot arms · ICRA 1988 |
Robotics › Motion planning and robot control › path planning
collision-free path planning |
0.0 | 1 | 1988 | Collision detection for planning collision-free motion of two robot arms · ICRA 1988 |
Robotics › Robot manipulation › dual-arm manipulation
dual-arm coordination |
0.0 | 1 | 1988 | Collision detection for planning collision-free motion of two robot arms · ICRA 1988 |
Robotics › Motion planning and robot control › motion planning › multi-robot motion planning
multi-arm motion planning |
0.0 | 1 | 1988 | Collision detection for planning collision-free motion of two robot arms · ICRA 1988 |
Hardware reliability and fault tolerance
error-correcting codes for memory |
0.0 | 2 | 1983 | Memory Package Error Detection and Correction · IEEE Trans. Computers 1983 Code Constructions for Error Control in Byte Organized Memory Systems · IEEE Trans. Computers 1983 |
Hardware reliability and fault tolerance
soft errors |
0.0 | 2 | 1990 | Unidirectional Byte Error Detecting Codes for Computer Memory Systems · IEEE Trans. Computers 1990 Code Constructions for Error Control in Byte Organized Memory Systems · IEEE Trans. Computers 1983 |
Hardware reliability and fault tolerance › error-correcting codes for memory
byte error correcting code |
0.0 | 1 | 1983 | Code Constructions for Error Control in Byte Organized Memory Systems · IEEE Trans. Computers 1983 |
Coding theory
error-correcting codes |
0.0 | 1 | 1983 | Memory Package Error Detection and Correction · IEEE Trans. Computers 1983 |
Hardware reliability and fault tolerance › memory fault tolerance
memory error detection |
0.0 | 1 | 1990 | Unidirectional Byte Error Detecting Codes for Computer Memory Systems · IEEE Trans. Computers 1990 |
Coding theory › error-correcting codes
cyclic codes |
0.0 | 1 | 1983 | Memory Package Error Detection and Correction · IEEE Trans. Computers 1983 |
Methods — techniques the papers use, named apart from their topics
coding theory · 0.0sphere model approximation · 0.0path replanning · 0.0hamming code · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2010 | Physical Layer Error Correction Based CipherabstractIn conventional communication systems, error correction is carried out at the physical layer while data security is performed performed at an upper layer. As a result, these steps are done as separate steps. As opposed to this conventional system, we present a scheme that combines error correction and data security as one unit so that both encryption and encoding could be carried out at the physical layer. Hence, in this paper, we present an Error Correction Based Cipher (ECBC) that combines error correction and encryption/decryption in a single step. Encrypting and encoding or decoding and decrypting in a single step will lead to a faster and more efficient implementation. One of the challenges of using previous joint schemes in a communications channel is that there is a tradeoff between data reliability and security. However in ECBC, there is no trade off between reliability and security. Errors introduced at the transmitter for randomization are removed at the receiver. Hence ECBC can utilize its full capacity to correct channel errors. We show the result of randomization test on ECBC and its security against conventional attacks. We also present the result of the FPGA implementation of the ECBC encryption. Oluwayomi B. Adamo, Shengli Fu, Murali R. Varanasi |
GLOBECOM | 3 |
| 2007 | Cooperative Network Coding for Wireless Ad-Hoc NetworksabstractIn wireless ad-hoc networks, a major challenge is how to provide robust and efficient communication. To achieve this goal, cooperative communication and network coding have been proven to be effective. In the literature, most existing studies focus on the performance of the two schemes separately. In our study, we will investigate the performance of system that combines them tightly together. In particular, we will propose a unified two-way traffic model that can characterize the features of both of them. Based on this model, we develop a new cooperative network coding scheme to further improve the system throughput. Both decode-and-forward and amplify-and-forward techniques are discussed for the two-way traffic model. Numerical results show that the new scheme can significantly improve the performance over traditional schemes. Shengli Fu, Kejie Lu, Yi Qian 0001, Murali R. Varanasi |
GLOBECOM | 4 |
| 1990 | Unidirectional Byte Error Detecting Codes for Computer Memory SystemsabstractCodes are developed for detecting unidirectional errors in t bytes simultaneously (t-UBED) while also providing all unidirectional error detection (AUED). These classes of codes differ from purely all unidirectional error detecting codes in that the errors in one byte may be of the form 1 to 0, while in another byte they may be of the form 0 to 1. The codes utilize 2 B for parity check information. As an example, a code providing 3-UBED+AUED protection for up to 12 information bytes of 8 b each can be constructed.> Larry A. Dunning, Gur Dial, Murali R. Varanasi |
IEEE Trans. Computers | 3 |
| 1988 | Collision detection for planning collision-free motion of two robot armsabstractThe authors focus on collision detection for planning collision-free motion of two robot arms in a common workspace. A collision-free motion is obtained by detecting collisions along the straight-line trajectories of the robots using a sphere model for the wrists and then replanning the paths and/or trajectories of one or both of the robots to avoid collisions. A novel approach to collision detection is presented and a discussion on collision avoidance is given.> Robert A. Basta, Rajiv Mehrotra, Murali R. Varanasi |
ICRA | 3 |
| 1983 | Code Constructions for Error Control in Byte Organized Memory SystemsabstractError correcting codes, such as Hamming codes, have been used successfully to correct errors arising from failures in computer memories. Failure of a chip or card can cause errors which exceed the capabilities of these codes. We construct codes which detect any byte error and correct such errors if they are single random errors. A subclass of the codes developed is shown to have the additional capability of detecting double errors. These codes are intended for use when data are packaged on a byte per chip or a byte per card basis. The codes require fewer check bits than any previously known to the authors except when the byte length or number of bytes is small. Larry A. Dunning, Murali R. Varanasi |
IEEE Trans. Computers | 2 |
| 1983 | Memory Package Error Detection and CorrectionabstractSingle error correcting-double error detecting (SEC-DED) codes have been successfully used in computer memories for reliability. In the present-day technology of very large scale integration storage arrays bit error correction as well as byte error detection/byte error correction become extremely important. We devise here classes of cyclic codes with generator of the form (xb -1) p(x) for some suitable irreducible polynomial p(x) which provide 1) single byte error correction (SBEC), and 2) single error correction, double error detection, and byte error detection (SEC-DED-BED) codes. The codes have high information rate and are easy to implement. This general class of codes combines elegantly the results of several researchers and in some cases extends their results. Murali R. Varanasi, T. R. N. Rao, Son Pham |
IEEE Trans. Computers | 1 |