With the growing complexity of todays ASICs and the number of designers involved in one VHDL ASIC project, the need for a VHDL development system together with coding rules for simulation and synthesis has emerged.This paper describes the VHDL Coding Standard which has been established and the VHDL development system including code entry, code formatting, code compliance checkers, data management and multi-user project set-up.

The design of the KISS-16V2, an ASIC DSP core incorporating an extremely flexible architecture, is described. It is a low-power, 1- mu m CMOS DSP with highly parallel architectural functions, and a sophisticated instruction set. This DSP was developed to provide an efficient integration of the multitude of functions required in a GSM (Groupe Speciale Mobile) hand held.>

This paper describes the modular test concept of the digital signal processor @SP) KISS-16V2 incorporating scan test, extensive use of BIST methods and boundary scan test, embedded in a JTAG environment to achieve an optimal fault coverage to cost ratio.

In this paper we present the ALGIC silicon compiler system. Starting from a structural and functional description of digital VLSI circuits, the system generates automatically the corresponding layout in a full custom design style. Main components of the ALGIC system are a system monitor module, a parameterisable macrocell generator, an appropriate floorplanner with 100% routing solution including planar VDD/GND trees and a block-oriented timing verifier. One essential feature of the system is the high degree of integration between all program modules using the concept of abstract data types. The flexibility and performance of the whole system is demonstrated by real design examples in the field of DSP applications.

The program SCAT is a new timing verifier within the ALGIC silicon compiler. It provides a precise assessment of the timing behaviour of the automatically generated LSI circuits by means of block-oriented statistical algorithms leading to a running time approximately linear to the number of circuit elements, which are emulated by delay time elements. Interconnect delays are handled by the same statistical model. Synchronous circuits are described by an appropriate coordinate transformation leading to an algorithm for the calculation of the minimum clock period. The special case of recursive structures is briefly mentioned.