Recent analog design tools have started to allow designers to archive not only the sized schematics but also some of the objectives that the circuit is trying to achieve. This paper first describes STAR (Schematic Tool for Analog Reuse), a system that captures designer's knowledge as part of the archival circuit representation, and then describes how this system can be used to create portable design modules. Creating portable analog modules require more than just the optimization criteria for the cell. It must also include the constraints on the cell's environment (for proper operation), and how these constraints should scale with technology. Furthermore, the system must help the designer in the current task of creating the design, since it is rare that a designer thinks about creating IP for someone else. We demonstrate the capability and utility of this system by examining the reuse of a phase-locked loop.

The authors present the architecture of a general-purpose broadband-ISDN (B-ISDN) switch chip and, in particular, its novel feature: the weighted round-robin cell (packet) multiplexing algorithm and its implementation in hardware. The flow control and buffer management strategies that allow the chip to operate at top performance under congestion are given, and the reason why this multiplexing scheme should be used under those circumstances is explained. The chip architecture and how the key choices were made are discussed. The statistical performance of the switch is analyzed. The critical parts of the chip have been laid out and simulated, thus proving the feasibility of the architecture. Chip sizes of four to ten links with link throughput of 0.5 to 1 Gb/s and with about 1000 virtual circuits per switch have been realized. The results of simulations of the chip are presented.>