A micropower, low-noise, bandpass amplifier for biomedical implants is presented. Operating at low frequency, the amplifier is fully integrated without any external passive components. Low-frequency noise and offset is reduced through the autozeroing technique. The autozeroing frequency and noise bandwidth is optimized to reduce noise folding. The design consists of a novel variable gain amplifier as the first stage, a low-Gm high-pass filter as the second stage, and a low-pass Gm-C amplifier as the last stage. Subthreshold operation is utilized in all input pair transistors to reduce power consumption, while a low-Gm OTA (operational transconductance amplifier) is realized with a current division technique. A cross-couple parallel pair of source degeneration transistors is utilized to increase the linearity crucial to neural spike detection. The design is realized in a CMOS 0.18mum process. It has an offset of 600muV, a variable gain from 42dB to 0dB, and 50 to 900Hz bandwidth while occupying 0.245mm2area. The total circuit consumes only 26muW in a 1.8V power supply; the input referred noise is estimated to be 5.6muVrms.

A novel charge-metering stimulus amplifier is proposed for high performance neural prosthesis stimulation. The new charge-based approach with feedback has low charge error 0.5%, low charge imbalance 0.2%, and high power efficiency. Charge-metering stimulus amplifier can be implemented using advanced 0.18mum CMOS technology and is compatible with mixed-signal system-on-a-chip (SoC) implantable devices. It also has the capability to monitor the electrode-tissue contact quality and estimate the interface impedance in real-time for robust stimulation.

The DIVA (Data IntensiVe Architecture) system incorporates a collection of Processing-In-Memory (PIM) chips as smart-memory co-processors to a conventional microprocessor. We have recently fabricated prototype DIVA PIMs. These chips represent the first smart-memory devices designed to support virtual addressing and capable of executing multiple threads of control. In this paper, we describe the prototype PIM architecture. We emphasize three unique features of DIVA PIMs, namely, the memory interface to the host processor, the 256-bit wide datapaths for exploiting on-chip bandwidth, and the address translation unit. We present detailed simulation results on eight benchmark applications. When just a single PIM chip is used, we achieve an average speedup of 3.3X over host-only execution, due to lower memory stall times and increased fine-grain parallelism. These 1-PIM results suggest that a PIM-based architecture with many such chips yields significantly higher performance than a multiprocessor of a similar scale and at a much reduced hardware cost.

Processing-in-memory (PIM) chips that integrate processor logic into memory devices offer a new opportunity for bridging the growing gap between processor and memory speeds, especially for applications with high memory-bandwidth requirements.The Data-IntensiVe Architecture (DIVA) system combines PIM memories with one or more external host processors and a PIM-to-PIM interconnect.DIVA increases memory bandwidth through two mechanisms: (1) performing selected computation in memory, reducing the quantity of data transferred across the processor-memory interface; and (2) providing communication mechanisms called parcels for moving both data and computation throughout memory, further bypassing the processor-memory bus.DIVA uniquely supports acceleration of important irregular applications, including sparse-matrix and pointer-based computations.In this paper, we focus on several aspects of DIVA designed to effectively support such computations at very high performance levels: (1) the memory model and parcel definitions; (2) the PIM-to-PIM interconnect; and, (3) requirements for the processor-to-memory interface.We demonstrate the potential of PIMbased architectures in accelerating the performance of three irregular computations, sparse conjugate gradient, a natural-join database operation and an object-oriented database query.