Abstract Versatile Video Coding (VVC) is the latest video coding standard established by ISO and ITU-T, boasting a doubled coding efficiency compared to previous standards. However, this substantial enhancement in coding efficiency comes at the cost of an increase in computational demands, posing challenges for practical implementations. This paper conducts a thorough and quantitative assessment of VVC inter-frame prediction, the most computationally intensive tool in the VVC encoder. A comprehensive set of experiments on inter-frame prediction is presented, with a detailed evaluation of the primary bottlenecks of this tool. To the best of the authors’ knowledge, this work is the first in the literature to offer this in-depth assessment of VVC inter-frame prediction.

This paper presents a fast Affine Motion Estimation (AME) of Versatile Video Coding (VVC) Standard, based on Machine Learning and using Random Forest (RF) classification method. This encoding approach develops an RF model for each block size. The models were trained with information extracted during the VVC encoding process of the current, parent, and neighboring Coding Units (CU). Each model is applied to predict whether the Affine Motion Estimation (AME) will be skipped or not for that CU size. The proposed solution achieves a reduction of 20% on average in AME encoding time, with an insignificant impact of 0.07% on BD-BR.

This paper presents a fast transform decision scheme for Versatile Video Coding (VVC) intra-frame prediction using decision trees. VVC introduces several novel coding tools to improve the coding efficiency of the intra-frame prediction at the cost of a high computational effort, including a new transform coding process using Multiple Transform Selection (MTS) for primary transform and Low-Frequency Non-Separable Transform (LFNST) for secondary transform. We developed an efficient complexity reduction scheme composed of two solutions based on decision tree classifiers to avoid the MTS and LFNST evaluations in the costly Rate-Distortion optimization (RDO) process. Experimental results showed that the proposed scheme provides 11% of encoding timesaving with a negligible impact on the coding efficiency.

This article presents a configurable fast block partitioning decision for Versatile Video Coding (VVC) intra-frame prediction using Light Gradient Boosting Machine (LGBM). VVC further improves the coding efficiency by introducing a Quadtree with nested Multi-Type Tree (QTMT), enabling five split types allowing square and rectangular Coding Unit (CU) sizes. However, this improvement in the coding efficiency comes at the cost of a high computational burden since several combinations of block sizes and prediction modes are evaluated through the costly Rate-Distortion Optimization (RDO) process. In this article, we propose a partitioning decision using LGBM classifiers to avoid the exhaustive RDO process and skip the evaluation of split types that are unlikely to be chosen as the best one. For this purpose, five classifiers (one for each split type) were offline trained with an efficient training process and using effective features of texture, coding, and context information. The proposed solution is highly configurable and can provide several operation points with different tradeoffs between timesaving and coding efficiency, according to the application requirements. Considering five operation points, the configurable solution can reduce the encoding time from 35.22% to 61.34%, with coding efficiency losses from 0.46% to 2.43%. Compared to the state-of-the-art, our solution is able to outperform the related works in terms of combined rate-distortion and timesaving.

This paper presents an encoding time and encoding efficiency analysis of the Quadtree with nested Multi-type Tree (QTMT) structure in the Versatile Video Coding (VVC) intra-frame prediction. The QTMT structure enables VVC to improve the compression performance compared to its predecessor standard at the cost of a higher encoding complexity. The intra-frame prediction time raised about 26 times compared to the HEVC reference software, and most of this time is related to the new block partitioning structure. Thus, this paper provides a detailed description of the VVC block partitioning structure and an in-depth analysis of the QTMT structure regarding coding time and coding efficiency. Based on the presented analyses, this paper can guide outcoming works focusing on the block partitioning of the VVC intra-frame prediction.

This paper presents a learning-based complexity reduction scheme for Versatile Video Coding (VVC) intra-frame prediction. VVC introduces several novel coding tools to improve the coding efficiency of the intra-frame prediction at the cost of a high computational effort. Thus, we developed an efficient complexity reduction scheme composed of three solutions based on machine learning and statistical analysis to reduce the number of intra prediction modes evaluated in the costly Rate-Distortion Optimization (RDO) process. Experimental results demonstrated that the proposed solution provides 18.32% encoding timesaving with a negligible impact on the coding efficiency.

The decrease of the performance gain dictated by Moore's Law boosted the development of manycore architectures to replace single-core architectures. These new architectures must employ parallel applications and distribute its workload over a multitude of cores to reach the desired performance. Parallel applications are harder to develop than sequential ones since the developer must guarantee data integrity using synchronization primitives. While multiple novel solutions have been proposed to speed up parallel applications through handling one type of data synchronization primitive, exceptionally few works support multiple types of synchronization primitives and legacy code. This article proposes Subutai, a hardware/software co-design solution for accelerating multiple synchronization primitives without modifying the application source code. By providing a new user library, while retaining an existing synchronization API, legacy and novel applications can benefit from our solution. Our experimental evaluation, which provides a POSIX Threads implementation, demonstrates Subutai speeds up to 2.71× and 4.61× the execution of single- and multiple-application executions, respectively.

This Work in Progress-Research to practice paper introduces the development of a Project Based Learning course on Analog Circuits. This is a six-credit course of fourteen weeks duration, designed for undergraduate students of Electrical and Electronics Engineering. This paper presents the course structure, project planning and feedback from students. The experience gained by designing and implementing this course will be used to develop improved courses for higher semesters for this batch of students. The overall objective is to help students to design Analog Circuits using discrete electronic components and simple integrated circuits and sensitize them on sustainability goals like power saving by using low power and low-cost components, optimized designs, standard practices and solutions that are useful for society. The Goals, Activities, Products and Assessment (GAPA) for the course are interlinked and logistics planning has been done before the commencement of the semester. The curriculum has been developed to cover the concepts required for developing sustainable products, and the topics discussed involve low power amplifiers, oscillators, wave shaping circuits and filters. The students registered for this course have experienced PBL in their previous semesters and have successfully completed a prerequisite course named Fundamentals of Automation Engineering. They are skilled on using the electronic test and measurement equipment, designing Printed Circuit Boards (PCB) and soldering of electronic components on the boards. Although they are granted autonomy in selecting components and circuit design, project goals are identified by the instructor and evaluation weightage assigned consciously to these goals. Activities are conducted during sessions to help students learn the concepts required for the gradually developing the project. Feedback is required from the students to compare the planned goals versus achieved goals and is analyzed for pluses and deltas. It is also used to monitor the motivation of students, to make the course more interesting for intrinsic learning.

Versatile Video Coding (VVC) is the next-generation of video coding standards, which was developed to double the coding efficiency over its predecessor High-Efficiency Video Coding (HEVC). Several new coding tools have been investigated and adopted in the VVC Test Model (VTM), whose current version can improve the intra coding efficiency by 24% at the cost of a much higher coding complexity than the HEVC Test Model (HM). Thus, this paper provides a detailed VVC intra coding complexity analysis, which can support upcoming works for finding the most timeconsuming tool that could be simplified to achieve a real-time encoder design.

This paper presents a fast partitioning decision scheme for Versatile Video Coding (VVC) intra prediction. VVC adopts the tree coding block structure named Quadtree with nested Multi-Type (QTMT), which significantly improves the coding efficiency at the cost of a high computational effort, limiting its adoption for real applications. Thus, we developed a scheme that encompasses two strategies exploring the features of the current block and the encoding context through the selected intra prediction mode to skip unnecessary evaluations of binary and ternary partitions. Experimental results, obtained with VVC Test Model 5.0 and considering the Common Test Conditions (CTC) under All-Intra (AI) encoder configuration, demonstrated that the proposed scheme achieves 31.41% of coding time saving, on average, with negligible coding efficiency loss.

This paper presents a fast depth map encoding for 3D-High Efficiency Video Coding (3D-HEVC) based on static decision trees. We used data mining and machine learning to correlate the encoder context attributes, building the static decision trees. Each decision tree defines that a depth map Coding Unit (CU) must be or not be split into smaller blocks, considering the encoding context through the evaluation of the encoder attributes. Specialized decision trees for I-frames, P-frames and B-frames define the partitioning of 64 × 64, 32 × 32, and 16 × 16 CUs. We trained the decision trees using data extracted from the 3D-HEVC Test Model considering all-intra and random-access configurations, and we evaluated the proposed approach considering the common test conditions. The experimental results demonstrated that this approach can halve the 3D-HEVC encoder computational effort with less than 0.24% of BD-rate increase on the average for all-intra configuration. When running on random-access configuration, our solution is able to reduce up to 58% the complete 3D-HEVC encoder computational effort with a BD-rate drop of only 0.13%. These results surpass all related works regarding computational effort reduction and BD-rate.

This paper presents the Tile Timing-Aware balancing algorithm (TITAN) for speeding up the 3D-High Efficiency Video Coding (3D-HEVC) video encoding. The design of the TITAN algorithm is based on the premise that the encoding time of tiles partitioning of neighbor frames are similar. Therefore, based on the encoding time of the last-encoded frame, TITAN controls the tiles boundaries aiming to maximize the balance among tiles. Our software evaluation with TITAN implemented in 3D-HEVC Test Model 16.0 achieved an average of 6.2% higher speedup compared to the uniform-sized tiles. This is the first work in the literature proposing to speed up the 3D-HEVC video encoding by balancing the tiles workload.

The depth maps intra-frame prediction of 3D High Efficiency Video Coding (3D-HEVC) inherits all texture encoding techniques provided by HEVC and provides new coding tools for depth map predictions. These tools comprise algorithms, such as bipartition modes, intra-picture skip, and DC-only. This paper details these tools and shows how they work together with the original HEVC algorithms in the depth map intra-frame prediction for allowing high-efficiency encoding. Besides, this paper analyzes the encoding time and the encoding mode distribution of the intra-frame prediction tools over different quantization scenarios. We aim to provide support for upcoming works on depth map encoding, including complexity reduction and control, real-time embedded systems implementations, and even the development of improved tools to encode depth maps.

This paper presents a fast 3D-High Efficiency Video Coding (3D-HEVC) depth maps intra-frame prediction based on static Coding Unit (CU) splitting decisions trees. This coding approach uses data mining to extract the correlation among the encoder context attributes and to define a split decision tree for each CU level of the depth maps encoding. The decision trees were trained using the information extracted from 3D-HEVC Test Model (3D-HTM) and using the Common Test Conditions (CTC). Each decision tree defines if the current CU must be split into smaller sizes, considering the encoding context through the evaluation of some current encoder attributes. The proposed solution reaches a complexity reduction of 59.0% for depth maps coding with a negligible impact of 0.18% in the encoding efficiency of synthesized views.

This work proposes the Dynamically Configurable 3D-HEVC Depth Maps Intra-Frame Prediction (DCDM-Intra), which explores the fact that Rough Mode Decision (RMD) was inherited from texture coding without taking advantages of the depth maps simplicity. DCDM-Intra classifies the HEVC Intra-frame Prediction Modes (IPMs) according to their BD-rate impact when encoding depth maps. Then, the application or the user can dynamically define the number of IPMs supported by the depth maps intra-prediction, according to the system status or application requirements, removing the IPMs that less affect the encoding efficiency. DCDM-Intra allows 35 distinct operation points with different encoding efficiency impacts. Experimental results demonstrate that the exclusion of 20% of IPMs causes a BD-rate increase of 0.03%, and the removal of almost 51% of IPMs rises 0.11% the BD-rate.

This paper presents an efficient hardware design for the Depth Modeling Mode 1 (DMM-1) decoder of the 3D-High Efficiency Video Coding (3D-HEVC). The designed architecture uses a lossless wedgelet memory compression technique to reduce the used memory, and a well-balanced parallelism level to allow the desired throughput at the minimum possible power consumption and area usage. The architecture was synthesized for the 65nm ST standard cells technology, using 4,047 gates and consuming 0.95mW. It is capable of processing 1080p videos at 30 frames per second, decoding all allowed block sizes and wedgelets patterns. Besides, the proposed architecture saves 10.7% of area and 29.1% of power when compared with a version without memory compression. At the best of the author's knowledge, this is the first work with a dedicated hardware design targeting the DMM-1 decoder.

This paper presents a complexity reduction technique for 3D High Efficiency Video Coding (3D-HEVC) using Rate-Distortion (RD) list reduction in the depth maps intra-frame prediction. In the 3D-HEVC standardization, the HEVC intra-frame prediction was inherited from texture to depth maps. However, considering depth maps simpler behavior than texture, the intra-frame prediction contains an unnecessary complexity since there is a high number of modes evaluated by their RD-cost. This paper evaluates the usage of fewer best-ranked modes in RD-list. As a case study, 23.9% of complexity reduction was achieved by reducing the Rough Mode Decision (RMD) selection and the Most Probable Modes (MPM) algorithm to the selected configuration with small impact in BD-rate.

This paper presents a qualitative discussion of the depth maps properties that can be considered to achieve complexity reduction for 3D-High Efficiency Video Coding (3D-HEVC) depth maps coding. Both intra and inter-frame predictions are considered in this discussion that conduced to the proposition of two simple complexity reduction techniques: the Simplified Edge Detector (SED) and the Diamond Search (DS) simplified inter-prediction. The SED anticipates the blocks that are likely to be better predicted by the HEVC intra-prediction, avoiding evaluations of Depth Modeling Modes (DMM). The DS and SED were compared to anchor results and experimental analysis showed that the proposed algorithms are able to achieve a time saving of 11.3% encoding time reduction, with acceptable impact on the BD-Rate of the synthesized views of 0.6%.

This paper presents a new mode decision for the depth maps intra-frame prediction in 3D-HEVC. The proposed technique decides if the traditional High Efficiency Video Coding-based (HEVC) intra-frame prediction should be performed or skipped. This technique is inspired by the fact that traditional intra-frame prediction may generate artifacts in the synthesized views when an edge is encoded. The Simplified Edge Detector (SED) algorithm has been proposed to classify if a block contains an edge or a nearly constant region demanding a minimum processing overhead. Through software evaluations, SED algorithm was capable to obtain an average complexity reduction of 23.8% for depth maps coding with no quality losses.

This paper proposes a complexity reduction algorithm for the depth maps intra prediction of the emerging 3D High Efficiency Video Coding standard (3D-HEVC). The 3D-HEVC introduces a new set of specific tools for the depth map coding that includes four Depth Modeling Modes (DMM) and these new features have inserted extra effort on the intra prediction. This extra effort is undesired and contributes to increasing the power consumption, which is a huge problem especially for embedded-systems. For this reason, this paper proposes a complexity reduction algorithm for the DMM 1, called Gradient-Based Mode One Filter (GMOF). This algorithm applies a filter to the borders of the encoded block and determines the best positions to evaluate the DMM 1, reducing the computational effort of DMM 1 process. Experimental analysis showed that GMOF is capable to achieve, in average, a complexity reduction of 9.8% on depth maps prediction, when evaluating under Common Test Conditions (CTC), with minor impacts on the quality of the synthesized views.

In this paper the hardware friendly Multi Point Diamond Search (MPDS) motion estimation (ME) algorithm is evaluated in the High Efficiency Video Coding Standard (HEVC). The MPDS algorithm was implemented in HEVC reference software and its efficiency is compared with the standard HEVC fast algorithm, the Enhanced Predictive Zonal Search (EPZS). The evaluation result, in average, shows loses of only 1.7% in the compression rate and 0.05% in PSNR. However, the main advantage of the MPDS algorithm is its hardware friendly aspect and this paper also presents its hardware design focused on real time processing HD 1080p videos. The designed architecture is capable to process HD 1080p videos in real time when synthesized for TSCM 90nm technology. The MPDS algorithm has obtained a good tradeoff among quality, compression rate and costs for its hardware implementation.

This paper presents a dedicated hardware architecture for the Rotational Transform (ROT), which is one of the novel tools proposed for the emergent HEVC video coding standard. The main goal of this coding tool is to achieve higher energy compaction of the main transform coefficient matrix, minimizing the quantization error and improving the efficiency of the entropy encoding. Five versions of this architecture were implemented, using either a fully combinational structure or a pipeline with nine stages. The designed architectures were described in VHDL and synthesized for an Altera Stratix III FPGA. The synthesis results show that all versions can process very high resolution videos, such as QFHD, in real time. The version with the highest processing rate achieved a maximum operation frequency of 260.15 MHz. This architecture reaches a processing rate of 2.08 billion samples per second, allowing it to process UHDTV videos in real time.

This paper presents the Spread and Iterative Search (S&IS) motion estimation algorithm, which uses a random spread evaluation together with a central iterative evaluation to avoid local minima falls and to increase the image quality for high definition videos. Considering Full HD videos, S&IS reached an average PSNR gain of 1.41dB when compared to Diamond Search (DS), with an increase of about four times in the number of evaluated blocks. When compared to Full Search (FS), the S&IS achieved an average PSNR loss of 1.56 dB, evaluating 73 times less blocks than FS. An efficient architecture for the S&IS algorithm is also presented in this paper. The architecture was designed targeting in real time processing (30 frames per seconds) for QFHD videos (3840×2160 pixels). The architecture was described in VHDL and synthesized for and Altera Stratix 4 FPGA and for ST90nm standard cells technology. Booth syntheses show that the architecture is able to process QFHD frames in real time. The standard cells version is able to reach also a good trade-off among area, memory and power consumption, processing QFHD videos with 62.2 mW.

In this paper, we propose and investigate a new local search strategy for multiobjective memetic algorithms. More precisely, we suggest a novel iterative search procedure, known as theHill Climber with Sidestep(HCS), which is designed for the treatment of multiobjective optimization problems, and show further two possible ways to integrate the HCS into a given evolutionary strategy leading to new memetic (or hybrid) algorithms. The pecularity of the HCS is that it is intended to be capable both moving toward and along the (local) Pareto set depending on the distance of the current iterate toward this set. The local search procedure utilizes the geometry of the directional cones of such optimization problems and works with or without gradient information. Finally, we present some numerical results on some well-known benchmark problems, indicating the strength of the local search strategy as a standalone algorithm as well as its benefit when used within a MOEA. For the latter we use the state of the art algorithms Nondominated Sorting Genetic Algorithm-II and Strength Pareto Evolutionary Algorithm 2 as base MOEAs.

Hot forging of an Fe-Ni-Co alloy used for aeronautical purposes has been modeled using the commercial software ABAQUS™/Explicit in order to obtain all the mechanical and thermal information to proceed with piercing and ring rolling. The material used is a 909 Incoloy type super alloy and it is used for the energy generation industry. Information of the constitutive behaviour of the alloy was introduced into the package using experimental data from mechanical testing at different temperatures and strain rates. A thermo coupled analysis was carried out, temperature, stress and strain distributions were evaluated in order to use the results of the model for the further simulation of the ring rolling of the material.

In this paper we propose a novel iterative search procedure for multi-objective optimization problems. The iteration process -- though derivative free -- utilizes the geometry of the directional cones of such optimization problems, and is capable both of moving toward and along the (local) Pareto set depending on the distance of the current iterate toward this set. Next, we give one possible way of integrating this local search procedure into a given EMO algorithm resulting in a novel memetic strategy. Finally, we present some numerical results on some well-known benchmark problems indicating the strength of both the local search strategy as well as the new hybrid approach.