The multi-path commodity flow problem (MPCFP) is crucial for ensuring reliable and high-speed data transmission in communication networks. However, existing studies that employ pre-generated routing paths neglect real-time load state and the coupling among decisions, thus hindering the achievement of high-quality solutions. To overcome this, we propose Hierarchical Reinforcement Learning with Topology-Aware Exploration (HRL-TAE), which is the first fully end-to-end framework that dynamically produces high-quality solutions based on real-time network states. HRL-TAE integrates an exploration mechanism and utilizes the State Transition Guiding List (STGL) to guide state transitions, thereby transforming topology exploration into a Markov decision process. Guided by STGL, two closely coupled layers in HRL-TAE, that is, the path construct layer and the ratio allocate layer, construct multiple subpaths for each flow and allocate traffic ratios among them. Subsequently, adaptive constraint-driven masks exclude infeasible actions during decision making, thereby guaranteeing that all constraints are satisfied. We also adopt a tailored training approach to obtain accurate gradient estimates and improve training efficiency. Simulations and real-world experiments demonstrate that HRL-TAE achieves superior performance.

With technology scaling, process constraints and imperfections result in significant variation of post-Si performance and stability of SRAM from designed/target pre-Si parameters. Modification/ re-optimization of SRAM cell and/or tuning of process parameters to meet target performance and stability are limited by area constraints and involve several technology ramp-up cycles. For reducing access failures, if process is not fine tuned, memory access clock cycle period may need to be increased thereby compromising performance. We propose a design methodology to meet the target performance and reduce access failures by tuning the SRAM array peripherals instead of tuning the SRAM cell and process parameters. Proposed design methodology is supported by numerical framework and validated by simulation results on 45nm PDSOI technology. We further show that our methodology does not impact the READ stability of a cell.