Clock grids are often used in high-performance ASIC designs because of their low skew and robustness to variations. Resonant clock grids have the potential to reduce the power consumption of these high-performance clocks without sacrificing the skew and robustness of a clock grid. We present the first methodology to synthesize high-performance distributed resonant LC tank clock grids that utilize a pre-characterized inductor library. The use of a library reduces designer effort and total inductor area when compared with previous resonant clock grids while still attaining 59% power reduction and competitive skew when compared to traditional buffered clock grids.

Distributed iuductor-ca p acitor (LC) resouaut c1ock iug is a receut, promisiug techuique to reduce the euergy cousum p tiou iu Clock Distributiou Networks (CDNs) by recycliug the euergy ou-chi p .Eveu though the majority of power is saved, resouaut clocks distribute a siuusoidal clock sigual with a 25 % slew which iucreases short-circuit power iu the sequeutial elemeuts com p ared to traditioual buffered clocks.Iu this work, we preseut the first harmouic resouant clock circuit that adds a third harmonic to the fundamental frequency in order to iucrease the slew rate of resonant clocks and reduce the short circuit p ower in the sequential elements.We p resent two different methods of tuning a secondary tank circuit in a Colpitts oscillator to minimize the slew: one based on the frequency res p onse of the circuit and the other based on matching an ideal square wave clock signal.Both methods provide benefits in slew reduction at a modest cost of components. I. INTRODUCTIONClock distribution networks (CDN) can consume between 30-70% of total chip power in high-performance processors.Many techniques have been proposed to minimize the dynamic power including minimal wirelength routing, buffer/wire siz ing, low-voltage-swing, dynamic voltage and frequency scal ing, and clock gating.Many of these techniques exploit inactivity or reduced workloads to reduce power, but the fundamental limit during active modes is a severe challenge in future highly-threaded many-core and GPU processors.Resonant clock distributions are another alternative to save power that can recycle the energy on-chip.Various resonant

Clock meshes are extremely effective at producing low-skew regional clock networks that are tolerant of environmental and process variations. For this reason, clock meshes are used in most high-performance designs, but this robustness consumes significant power. In this work, we present two techniques to optimize high-performance clock meshes. The first technique is a mesh perturbation methodology for nonuniform mesh routing. The second technique is a skew-aware buffer placement through iterative buffer deletion. We demonstrate how these optimizations can achieve significant power reductions and a near elimination of short-circuit power. In addition, the total wire length is decreased, the number of required buffers is decreased, and both skew and robustness are improved on average when variation is considered.

Electromagnetic Interference (EMI) generated by electronic systems is increasing with operating frequency and shrinking process technologies. The clock distribution network is one of the major causes of on-chip EMI. In this paper, we discuss the EMI problem in clock tree design. Spectrum analysis shows that slew rate of clock signal is the main parameter determining the high-frequency spectral content distribution. This is the first work to consider maximum and minimum buffer slew rates in clock tree synthesis to reduce EMI. In this paper, we propose a dynamic programming algorithm to optimize the clock tree considering both traditional metrics and Electromagnetic Compatibility (EMC). Our experimental results show that slew can be controlled in a feasible range and high-frequency spectrum contents can be reduced without sacrificing the traditional metrics such as power and skew. With the efficient optimization and pruning method, the biggest benchmark is able to complete in four minutes.

Clock distribution networks can consume 35-70% of total chip power in high-performance designs [13]. Resonant clocks can potentially reduce this power by recycling the energy using on-chip inductors. We propose the first automated Resonant clOCK Synthesis (ROCKS) algorithm. Experimental results show that with 10% inductor area, clock power can be reduced by 34%. With more inductor area, up to 90% power savings is shown feasible.

Resonant clocking is a form of adiabatic clocking that retains much of the energy present in clock switching and recycles it into the following clock cycle. In this paper we present the first automated methodology using LC-assisted local clock buffers (LCLCB) for generating local resonant clocks. This uses a single-buffer single-inductor sector topology applied to non-uniform trees as found in most ASIC designs. We show that this form of adiabatic clocking can achieve power savings as much as 75% over traditional buffered clock networks.