The rapid advancement of generative models has increased the demand for generated image detectors capable of generalizing across diverse and evolving generation techniques. However, existing methods, including those leveraging pre-trained vision-language models, often produce highly entangled representations, mixing task-relevant forensic cues (causal features) with spurious or irrelevant patterns (non-causal features), thus limiting generalization. To address this issue, we propose CausalCLIP, a framework that explicitly disentangles causal from non-causal features and employs targeted filtering guided by causal inference principles to retain only the most transferable and discriminative forensic cues. By modeling the generation process with a structural causal model and enforcing statistical independence through Gumbel-Softmax-based feature masking and Hilbert-Schmidt Independence Criterion (HSIC) constraints, CausalCLIP isolates stable causal features robust to distribution shifts. When tested on unseen generative models from different series, CausalCLIP demonstrates strong generalization ability, achieving improvements of 6.83% in accuracy and 4.06% in average precision over state-of-the-art methods.

Homomorphic encryption (HE) has broad application prospects in the cloud computing security field. Efficient homomorphic computations of primitive circuits are critical for the applications of HE. However, existing implementation methods over plaintext do not fit well with those over ciphertext. To address this issue, a concise evaluation model is proposed to compare different implementation methods, using weighted computational complexity (WCC). The number, depth, and distribution of homomorphic multiplications are considered together in the model for the first time. In addition, two primitive binary circuits on homomorphically encrypted data are optimized by using a unit called dot multiplication (DotMC). A novel comparison circuit based on DotMC is presented, and the number of homomorphic multiplications is reduced from O(n log n) to O(n) without increasing the multiplicative depth compared with the logarithm comparison, where n is the bit length of the operand. The WCC of comparison is reduced from O(n( log n)2) to O(n( log n)). The carry-lookahead adder is optimized by moving some DotMCs to levels with smaller weight, which reflects the effect of the distribution of homomorphic multiplications on performance. Finally, the proposed DotMC is accelerated with a single-instruction-multiple-data approach for even one operation; the number of homomorphic multiplication is reduced from O(n) to O( log n) compared with other comparison with the same strategy. Various circuits with the size from 4 to 2048 b are implemented with HElib to prove the optimization for comparison and addition, as well as the effectiveness of the proposed model.

Large integer multiplication, or large degree polynomial multiplication, is the most time-consuming operation in fully homomorphic encryption (FHE). Low area and power consumption are difficult to maintain while achieving high performance for a large size multiplier. To address this issue, an area-efficient low-power architecture for multiplication, named NTTU, is proposed in this article. First, a combined number theoretic transform (NTT) method consisting of decimation-in-time (DIT) NTT for input in natural order and bit-reversed order is proposed to eliminate the steps of zero padding, scramble, and the first stage in NTT, thereby achieving a reduction of 7N/2 clock cycles compared with the single-type NTT method. Second, the NTT-uncoupled architecture is proposed to uncouple the multiplication components, decreasing the storage space for coefficients by 1/2 compared with state-of-the-art designs. Third, a parallel computing architecture based on a crossed memory access scheme is proposed, therein reducing the corresponding execution time by one-half compared with serial execution. Synthesized using 65 nm technology, the proposed architecture can multiply two 1024k/768k integers in 1.7 ms at 500 MHz at a cost of 13.66/7.67 million gates and 726.7/550.2 mW, and a 71.17 percent/ 30.37 percent area time product (ATP) reduction is achieved compared with the state-of-the-art ASIC designs.