Demo Data from VLDB 2026 / reviewers in the wild / expert
Lingfeng Pei
dblp:301/7999
· DBLP profile ↗
2ranked-venue papers
0as first author
2since 2021 · last 2024
0000-0002-2953-4650ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Network and information security
2 papers |
Hardware security and side channels · 67% Network security · 29% Cryptographic primitives and cryptanalysis · 4% | |
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Memory systems · 70% Processor architecture and microarchitecture · 30% |
Topics — the 8 heaviest of 10, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware security and side channels
microarchitectural side channel |
1.4 | 2 | 2024 | PREFETCHX: Cross-Core Cache-Agnostic Prefetcher-based Side-Channel Attacks · HPCA 2024 AfterImage: Leaking Control Flow Data and Tracking Load Operations via the Hardware Prefetcher · ASPLOS (2) 2023 |
Hardware security and side channels › microarchitectural side channel
prefetcher side channel |
1.4 | 2 | 2024 | PREFETCHX: Cross-Core Cache-Agnostic Prefetcher-based Side-Channel Attacks · HPCA 2024 AfterImage: Leaking Control Flow Data and Tracking Load Operations via the Hardware Prefetcher · ASPLOS (2) 2023 |
Network security
covert channel |
0.8 | 1 | 2024 | PREFETCHX: Cross-Core Cache-Agnostic Prefetcher-based Side-Channel Attacks · HPCA 2024 |
Network security › covert channel
cross-core covert channel |
0.8 | 1 | 2024 | PREFETCHX: Cross-Core Cache-Agnostic Prefetcher-based Side-Channel Attacks · HPCA 2024 |
Hardware security and side channels › side-channel leakage
control-flow leakage |
0.7 | 1 | 2023 | AfterImage: Leaking Control Flow Data and Tracking Load Operations via the Hardware Prefetcher · ASPLOS (2) 2023 |
Memory systems
cache |
0.2 | 1 | 2024 | PREFETCHX: Cross-Core Cache-Agnostic Prefetcher-based Side-Channel Attacks · HPCA 2024 |
Memory systems › memory hierarchy › cache hierarchy
last-level cache |
0.2 | 1 | 2024 | PREFETCHX: Cross-Core Cache-Agnostic Prefetcher-based Side-Channel Attacks · HPCA 2024 |
Processor architecture and microarchitecture › memory system microarchitecture
hardware prefetcher |
0.2 | 1 | 2023 | AfterImage: Leaking Control Flow Data and Tracking Load Operations via the Hardware Prefetcher · ASPLOS (2) 2023 |
Methods — techniques the papers use, named apart from their topics
side-channel attack · 1.5covert-channel attack · 1.5power side-channel attack · 1.3IP-stride prefetcher training · 1.3
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2024 | PREFETCHX: Cross-Core Cache-Agnostic Prefetcher-based Side-Channel AttacksabstractIn this paper, we reveal the existence of a new class of prefetcher, the XPT prefetcher, in modern Intel processors which has never been officially detailed. It speculatively issues a load, bypassing last-level cache (LLC) lookups, when it predicts that a load request will result in an LLC miss. We demonstrate that XPT prefetcher is shared among different cores, which enables an attacker to build cross-core side-channel and covertchannel attacks. We propose PREFETCHX, a cross-core attack mechanism, to leak users’ sensitive data and activities. We empirically demonstrate that PREFETCHX can be used to extract private keys of real-world RSA applications. Furthermore, we show that PREFETCHX can enable side-channel attacks that can monitor keystrokes and network traffic patterns of users. Our two cross-core covert-channel attacks also see a low error rate and a 122KiB/s maximum channel capacity. Due to the cache-independent feature of PREFETCHX, current cache-based mitigations are not effective against our attacks. Overall, our work uncovers a significant vulnerability in the XPT prefetcher, which can be exploited to compromise the confidentiality of sensitive information in both cryptography and non-cryptography-related applications among processor cores. Yun Chen 0004, Ali Hajiabadi, Lingfeng Pei, Trevor E. Carlson |
HPCA | 3 |
| 2023 | AfterImage: Leaking Control Flow Data and Tracking Load Operations via the Hardware PrefetcherabstractResearch into processor-based side-channels has seen both a large number and a large variety of disclosed vulnerabilities that can leak critical, private data to malicious attackers. While most previous works require speculative execution and the use of cache primitives to transmit data, our new approach, called AfterImage, requires neither, capitalizing on vulnerabilities in Intel’s IP-stride prefetcher to both expose and transmit victim data. By training this prefetcher with attacker-known values, and watching for changes to the prefetcher state when execution returns to the attacker, it is now possible to monitor and leak critical data from a large number of common userspace applications and kernel routines without speculation and additional cache accesses. To demonstrate the novel capabilities of AfterImage, we (1) present proof-of-concept attacks that leak data across different isolation levels, (2) present an end-to-end attack that leaks an entire RSA key from a modern, timing-balanced algorithm, and also (3) show how AfterImage can significantly improve the effectiveness of other attacks, such as power side-channel attacks, by using this technique as a high-precision marker. Yun Chen 0004, Lingfeng Pei, Trevor E. Carlson |
ASPLOS (2) | 2 |